Patents by Inventor Dewanshu Chhagan SEWAKE

Dewanshu Chhagan SEWAKE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Fractional phase locked loop (PLL) with digital control driven by clock with higher frequency than PLL feedback signal
    Patent number: 11764795
    Abstract: A phase locked loop (PLL) method includes generating a first signal based on a comparison of a phase of a reference clock or signal to a phase of a feedback clock; generating an output clock based on the first signal; generating an intermediate feedback clock including frequency dividing the output clock; fractionally frequency dividing the intermediate feedback clock based on a digital control signal to generate the feedback clock; and generating the digital control signal based on a sampling clock having a frequency greater than a frequency of the feedback clock. In one implementation, a PLL includes a frequency multiplier to generate the sampling clock based on the feedback clock. In another implementation, a PLL uses the intermediate feedback clock as the sampling clock.
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: September 19, 2023
    Assignee: QUALCOMM INCORPORATED
    Inventors: Burcin Serter Ergun, Julian Puscar, Zhiqin Chen, Dewanshu Chhagan Sewake
  • FRACTIONAL PHASE LOCKED LOOP (PLL) WITH DIGITAL CONTROL DRIVEN BY CLOCK WITH HIGHER FREQUENCY THAN PLL FEEDBACK SIGNAL
    Publication number: 20230170911
    Abstract: A phase locked loop (PLL) method includes generating a first signal based on a comparison of a phase of a reference clock or signal to a phase of a feedback clock; generating an output clock based on the first signal; generating an intermediate feedback clock including frequency dividing the output clock; fractionally frequency dividing the intermediate feedback clock based on a digital control signal to generate the feedback clock; and generating the digital control signal based on a sampling clock having a frequency greater than a frequency of the feedback clock. In one implementation, a PLL includes a frequency multiplier to generate the sampling clock based on the feedback clock. In another implementation, a PLL uses the intermediate feedback clock as the sampling clock.
    Type: Application
    Filed: November 29, 2021
    Publication date: June 1, 2023
    Inventors: Burcin Serter ERGUN, Julian PUSCAR, Zhiqin CHEN, Dewanshu Chhagan SEWAKE