Abstract: An impedance warping circuit (IWC) and technique for compensating the effect of a blocking capacitor within a transformer of an interface circuit for passing plain old telephone service (POTS) band and asynchronous digital subscriber line (ADSL) band signals on signals having frequencies in the POTS band. The IWC does not significantly affect the performance of the interface circuit in the ADSL band. The IWC synthesizes impedance to compensate the frequency-dependent deviation in the termination impedance across the tip/ring lines. The resulting termination impedance may be designed to conform to the Telcordia Standard of 900 ?+2.16 ?F or other telecommunication standards throughout the entire POTS band.

Abstract: An impedance warping circuit (IWC) and technique for compensating the effect of a blocking capacitor within a transformer of an interface circuit for passing plain old telephone service (POTS) band and asynchronous digital subscriber line (ADSL) band signals on signals having frequencies in the POTS band. The IWC does not significantly affect the performance of the interface circuit in the ADSL band. The IWC synthesizes impedance to compensate the frequency-dependent deviation in the termination impedance across the tip/ring lines. The resulting termination impedance may be designed to conform to the Telcordia Standard of 900 &OHgr;+2.16 &mgr;F or other telecommunication standards throughout the entire POTS band.

Abstract: Resistive circuits are provided at the tip and ring of the battery feed circuit as a method of alleviating the need for bulky DC transformers or complex integrated circuitry. The voltage is monitored through a set of comparators eliminating the expense of maintaining fused resistors. The voltages for voice or data transmission is amplified prior to being transmitted. Received signals are AC coupled, with proper biasing, onto the tip and ring lines. Any AC noise on the tip and ring line is shifted 180 degrees out of phase and re-inserted on the line to cancel the noise. As an enhancement to the battery feed circuit, another voltage comparator is added to check the line for DC current signifying an off hook condition.

Abstract: To accurately detect the short bursts of distinctive ringing signals within 100 milliseconds, a magnitude comparator produces a binary signal indicative of whether the instantaneous tip-ring voltage exceeds a predetermined magnitude. The binary signal is integrated over a predetermined period of time controlled by a timer. If the time integral is below a first predetermined value, the absence of ringing is detected; if above a second predetermined value, ringing is detected; if in between, the integrating interval is extended until the integral falls outside the two values.

Abstract: To produce a high current carring inductor with a high inductance value in space normally too small, a transformer is chosen which meets space requirements and has a primary winding of sufficient current capacity, but too little inductance. A bidirectional current source drives the secondary winding under control of a feedback circuit in response to sensed primary winding current to effectively multiply the primary winding inductance.

Abstract: A relay load is connected in the collector path of a first transistor (Q1) of high current carrying capacity. A second transistor (Q2) of similar conductivity type is effectively coupled across the first transistor. The bases of said first and second transistors are connected together. A current mirror circuit (Q3-Q6) is coupled from the collector of said second transistor to said bases to provide the additional base drive necessary to drive the first transistor towards saturation regardless of its Beta when maximum load current is required. The mirror circuit is designed so that the effects of transistor V.sub.be mismatches in the mirror are minimized.

Abstract: A telephone line circuit comprises a transformer that has a primary (13) and a secondary (14) winding. A low resistance (15) is connected in series with the primary winding. An amplifier circuit (17) is coupled across the resistance and serves to develop a predetermined dc control voltage. This control voltage is used to establish a dc current flow in the secondary which is n times that of any dc current flow in the primary, where n is the transformer turns ratio. The dc current flow established in the secondary is in a direction opposite that of the dc current flow in the primary. A second amplifier circuit (31, 36, 23) is coupled across the primary winding and serves to generate an ac control signal which is also delivered to the secondary winding to create a predetermined ac termination impedance.

Abstract: The disclosed operational amplifier comprises a first pair of complementary type transistors that have their emitter-collector paths connected in series across a source of reference potential. The emitters of the transistors are connected together and to an output terminal. A feedback resistance is coupled from the output terminal to the amplifier input. A second pair of complementary type transistors are similarly connected across said reference potential, with the emitters thereof connected together and to a second output terminal. A second feedback resistance is coupled from the second output to the amplifier input. A pair of resistors of predetermined values are respectively connected between the base electrodes of similar type transistors of the first and second transistor pairs. And a pair of constant current sources are respectively coupled to the base electrodes of the second pair of transistors.

Abstract: The battery feed circuit (FIG. 3) provides a balanced dc feed current (I.sub.TR) to a 2-wire telecommunications path. The dc current in each conductor is generated by a bidirectional current source (103 or 104) which is responsive to one of a complementary pair of first control signals (S.sub.1, S.sub.1) along with a second control signal (S.sub.2). The complementary pair of first control signals is generated by a feedback circuit (105) which monitors the differential mode voltage (V.sub.TR) across the path. To reduce power consumption, the complementary pair of first control signals is a nonlinear function of the differential mode voltage. The resulting battery feed profile (FIG. 2) reduces the current on short path lengths. Longitudinal balance is provided by the second control signal which varies the currents generated by each bidirectional current source by equal amounts. This second control signal is generated by a second feedback circuit (109) which monitors the common mode voltage across the path.

Abstract: The disclosed operational amplifier comprises a first pair of complementary type transistors (Q5, Q6) (of high current carrying capacity) that have their emitter-collector paths connected in series across a source of reference potential. The emitters of the transistors are connected together and to an output terminal (17). A second pair of complementary type transistors (Q3, Q4) are coupled across said reference potential, each transistor of said second pair being coupled across the similar conductivity type transistor of said first pair. A first pair of resistances (R1, R2) of predetermined value are respectively connected between the bases of the similar conductivity type transistors of said first and second pair. A second pair of resistances (R3, R4) respectively connect the emitters of the transistors of said second pair to said output terminal.

Abstract: A reduction in idle channel noise and crosstalk in a mid-riser-biased successive approximation encoder is achieved through the use of two polarity decisions. Encoder (401) assigns a sampled analog input signal to the closest one of a multitude of discrete signal levels or code steps. A comparator (109) provides this assignment by successive comparisons of the sampled signal with a series of reference signals (110). Each comparison produces a binary digit. The first comparison, or polarity decision, is not transmitted and instead coupled to feedback circuitry (401) to reduce any dc component in the analog input signal to substantially zero. A second polarity decision is then made using a non-zero offset reference signal (402) corresponding to an intermediate position on a code step, typically the midpoint. The non-zero offset reference signal is applied along with subsequent reference signals to the comparator to determine the closest code step.