Abstract: A system for detecting phase lock loss between first and second two level signals S.sub.N and S.sub.R, and comprising an Exclusive OR (XOR) gate having first and second input terminals and an output terminal, logic for supplying S.sub.N and S.sub.R to the first and second inputs of the XOR gate so that the center points of the respective upper and lower levels are aligned and with the time intervals between adjacent leading and trailing edges of S.sub.N and S.sub.R being nominally equal to .DELTA.t. Also provided is an AND gate having first and second input terminals and an output terminal, and delay logic for supplying the output signal of the XOR gate to the two input terminals of the AND gate with such output signal arriving at one of the input terminals of the AND gate a time interval .DELTA.t after the arrival of the output signal at the other input terminal of the AND gate and a detector for detecting an output signal from the AND gate to indicate loss of phase lock.