Abstract: Embodiments of the present disclosure provide an array substrate and a display panel. The array substrate includes a first active layer, a gate electrode, a gate insulating layer, a second active layer, and a source/drain metal layer. The first active layer is connected in parallel with the second active layer through a conductor layer. Through an active layer structure with two layers in parallel, an on-state current and mobility of equivalent carriers of a device are effectively improved, and a comprehensive performance of the device is improved.

Abstract: An array substrate and a display panel are provided. The array substrate includes an active layer. The active layer includes a channel portion and a doped portion. The doped portion includes a first doped layer and a second doped layer. The channel portion includes a first channel portion and a second channel portion. The first channel portion is connected to the first doped layer. The second channel portion is connected to the second doped layer. A part of the second channel portion overlaps with a part of the first doped layer, thus, a step-laminated structure is formed, and an overall performance of the device is improved.

Abstract: A semiconductor device and an electronic device are provided. The semiconductor device includes an insulating substrate and a thin film transistor layer. The thin film transistor layer includes a first active layer and a first insulating layer disposed on the first active layer, and a convex portion is formed on the first insulating layer. The thin film transistor layer further includes a second active layer and a third active layer disposed on both sidewalls and an upper surface of the convex portion, one end of the first active layer is connected to the second active layer, and another end of the first active layer is connected to the third active layer.

Abstract: The present application provides a thin film transistor substrate and an electronic device. The thin film transistor substrate includes: a substrate; a boss including an undercut structure, the undercut structure is located on a side wall of the boss; a filler located in the undercut structure; and an active layer located on the boss and the substrate, the active layer includes a channel, and the channel covers the undercut structure and the filler.

Abstract: Embodiments of the present disclosure provide a display panel and a display terminal. The display panel includes at least one ultraviolet sensing transistor and at least one control transistor disposed on a substrate, and a color film substrate including a light blocking unit; wherein the ultraviolet sensing transistor includes an ultraviolet absorbing layer, and an orthographic projection of the light blocking unit on the substrate covers an orthographic projection of the ultraviolet absorbing layer on the substrate. According to the embodiment of the present disclosure, the light blocking unit absorbs or blocks the visible lights to prevent the visible lights from entering into the ultraviolet absorbing layer.

Abstract: A fingerprint collection device and a display panel are provided. The fingerprint collection device includes: a base substrate, a driving circuit layer, a first passivation layer, a photodiode, a second passivation layer, and an electrode layer. A first electrode portion is electrically connected to the photodiode through a second via. A second electrode portion is electrically connected to a first signal trace and a second signal trace through a third via and a fourth via to form a bridge structure. Since the third via, the fourth via, and the second via are formed in same process, one process can be saved.

Abstract: A display panel and a manufacturing method thereof, and a display device are provided. The display panel includes a backlight module and an array substrate. The array substrate includes an insulation structure is located in the opening region. A first groove is defined at a side of the insulation structure away from the backlight module. A first insulation layer and a second insulation layer are filled in the first groove. The second insulation layer is located on a side of the first insulation layer close to the backlight module, and a refractive index of the second insulation layer is less than a refractive index of the first insulation layer.

Abstract: The present disclosure provides a vertical inverter and a semiconductor device including the vertical inverter, and the vertical inverter includes an insulation substrate, a first thin film transistor, and a second thin film transistor. By a layered arrangement of the first and second thin film transistors of the vertical inverter, more thin film transistors can be arranged within the limited space, so that the integration degree of the thin film transistors in the semiconductor device can be improved.

Abstract: An array substrate and a manufacturing method thereof are provided. The array substrate includes a thin film transistor layer including a first thin film transistor and an infrared detection element disposed on a first side of the thin film transistor layer. The infrared detection element includes a first electrode, a light-absorbing layer, and a second electrode sequentially stacked, wherein the infrared detection element is electrically connected to the first thin film transistor, and wherein a material of the light-absorbing layer is microcrystalline silicon. A thickness and band gap of the microcrystalline silicon simultaneously fulfill a purpose of infrared detection.

Abstract: An array substrate and a display panel are provided. The array substrate includes a substrate, an array layer, an inorganic insulation layer, a conductive electrode, a passivation layer, and a pixel electrode disposed in sequence. The array layer includes a source electrode and a drain electrode. A first via hole is defined in the array substrate. The first via hole penetrates the passivation layer and the inorganic insulation layer and exposes the drain electrode. The pixel electrode is connected to the drain electrode in the first via hole.

Abstract: A thin-film transistor (TFT) having a vertical structure and an electronic device are provided. The TFT having the vertical structure includes an insulating substrate and an active layer disposed on the insulating substrate. The active layer includes a first conductive part, an active section, and a second conductive part which are stacked. An orthographic projection of the first conductive part on the insulating substrate partly overlaps an orthographic projection of the second conductive part on the insulating substrate. Therefore, contamination ions may be prevented from entering the active section from the insulating substrate during manufacturing processes of the TFT. Thus, reliability of performance of the TFT may be improved.

Abstract: A semiconductor device and an electronic device are provided. The semiconductor device includes an insulating substrate, and a non-planar layer disposed on the insulating substrate and including a non-planar structure. The non-planar structure includes a sidewall. An active pattern is configured with at least a part located on the sidewall of the non-planar structure. The active pattern includes a channel located on the sidewall. A ratio of a size of the non-planar structure in a thickness direction of the non-planar layer to a thickness of the active pattern is less than or equal to seven.

Abstract: The present application provides a display panel and a display device. The display panel includes an array substrate, a color filter substrate, and a colloid layer. The array substrate includes a thin film transistor layer and a passivation layer. The passivation layer includes at least one first connection element. The color filter substrate is disposed opposite to the array substrate. The colloid layer is arranged between the passivation layer and the color filter substrate, the colloid layer is connected to the first connection element, and the colloid layer and the first connection element couple the array substrate to the color filter substrate.

Abstract: The present application discloses a display panel and an electrical terminal. The display panel includes: an underlay; an array driver layer located on the underlay and including a gate electrode layer and a source and drain electrode layer; a signal line including an adaptor portion located in the non-display region, wherein the adaptor portion includes a first wire section disposed in a same layer with the gate electrode layer, a second wire section disposed in a same layer with the source and drain electrode layer, and a bridge portion electrically connected to the first wire section and the second wire section; wherein the first wire section, the second wire section, and the bridge portion are disposed in different layers.

Abstract: In an array substrate of the present invention, only two insulating layers are arranged on a planarization layer. Compared with conventional techniques that require at least four insulating layers arranged on the planarization layer, a number of the insulating layers arranged on the planarization layer is reduced. Therefore, a number of photomasks is reduced in a manufacturing process of the array substrate, and the manufacturing process is simplified. The present invention also provides a manufacturing method of the array substrate, and a display panel.

Abstract: A display panel, an array substrate, and a manufacturing method thereof, wherein the array substrate includes a thin film transistor device, and an interface layer, a first transparent conductive layer, a passivation layer, and a second transparent conductive layer which are formed on the thin film transistor device in sequence. By replacing a planarization layer in the prior art with the interface layer, performing a gate re-etching process, and perforating the interface layer and the passivation layer to simultaneously form a deep via and a shallow via, a number of photomasks required to form the array substrate is reduced to 8. It effectively reduces costs of production materials and costs of photomasks.

Abstract: An array substrate, a manufacturing method thereof, and a display device are provided. The array substrate includes a substrate, a metal electrode layer, a first passivation layer, a first electrode layer, a photosensitive semiconductor layer, a second passivation layer, and a second electrode layer. The first electrode layer and the photosensitive semiconductor layer are both disposed on a surface of the first passivation layer away from the metal electrode layer.

Abstract: The embodiment of the present application discloses an array substrate, a display panel, and an electronic device. The array substrate includes a substrate and includes a control element; a first electrode is connected to the control element; a PIN diode is arranged on the first electrode, The PIN diode covers at least a part of the semiconductor layer of the control element and a part of the first electrode; a second conductive layer is arranged on the PIN diode, and the second conductive layer includes a second electrode.

Abstract: An array substrate, a display panel, and a display device are provided by the present application. The array substrate includes a base substrate; a light-sensitive component layer disposed on the base substrate, wherein a plurality of light-sensitive components are disposed at intervals in the light-sensitive component layer; and a first light-shielding layer disposed on the light-sensitive component layer. An orthographic projection of the first light-shielding layer on the base substrate partially overlaps with an orthographic projection of each of the light-sensitive components on the array substrate.

Abstract: An array substrate, a manufacturing method thereof, and a display device are provided. The array substrate includes a substrate, a metal electrode layer, a first passivation layer, a first electrode layer, a photosensitive semiconductor layer, a second passivation layer, and a second electrode layer. The first electrode layer and the photosensitive semiconductor layer are both disposed on a surface of the first passivation layer away from the metal electrode layer.