Patents by Inventor DEWEN LI

DEWEN LI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10949242
    Abstract: Disclosed by the present invention are a running method for an embedded type virtual device and a system, an embedded type device being divided into a managing process, a plurality of real-time modules and a plurality of non-real-time modules. The managing process reading a configuration file, loading real-time and non-real-time module libraries of each processor and completing initialization interaction by means of a virtual controller area network (CAN) bus and first in, first out (FIFO) communication. The managing process starting a real-time thread and serially scheduling real-time task according to a task period setting relation. The managing process starting a plurality of non-real-time threads, calling a period task of a non-real-time module and carrying out parallel communication with a plurality of debugging clients. The real-time modules exchange data with each other by means of a virtual data bus, and the real-time modules exchange data with the non-real-time modules by means of a sharing memory.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: March 16, 2021
    Assignees: NR ELECTRIC CO., LTD, NR ENGINEERING CO., LTD
    Inventors: Hongjun Chen, Qiang Zhou, Jifeng Wen, Jiuhu Li, Dongfang Xu, Guanghua Li, Wei Liu, Dewen Li, Lei Zhou, Tianen Zhao
  • Patent number: 10637287
    Abstract: An apparatus and method for ensuring the reliability of a trip protection of an intelligent substation. The apparatus comprises a main CPU and an auxiliary CPU connected together, and a main FPGA and an auxiliary FPGA connected together. The main FPGA and the auxiliary FPGA are connected to a physical layer of a protection apparatus, and the main CPU and the auxiliary CPU are connected to a state monitoring data output end of a protected device. The main CPU sends a processing result to the main FPGA, the auxiliary CPU sends the processing result to the auxiliary FPGA, and the auxiliary FPGA synchronizes current information with the main FPGA after receiving information sent by the auxiliary CPU. When the main FPGA receives trip information, the main FPGA comparing the consistency of current trip information obtained from the main CPU with current trip information obtained from the auxiliary FPGA.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: April 28, 2020
    Assignees: NR ELECTRIC CO., LTD, NR ENGINEERING CO., LTD
    Inventors: Zongguang Xu, Jifeng Wen, Yong Chen, Xiang Li, Yan Li, Yucan Zhao, Ming Yuan, Qiang Zhou, Guanghua Li, Tianen Zhao, Dewen Li
  • Publication number: 20190317791
    Abstract: Disclosed by the present invention are a running method for an embedded type virtual device and a system, an embedded type device being divided into a managing process, a plurality of real-time modules and a plurality of non-real-time modules. The managing process reading a configuration file, loading real-time and non-real-time module libraries of each processor and completing initialization interaction by means of a virtual controller area network (CAN) bus and first in, first out (FIFO) communication. The managing process starting a real-time thread and serially scheduling real-time task according to a task period setting relation. The managing process starting a plurality of non-real-time threads, calling a period task of a non-real-time module and carrying out parallel communication with a plurality of debugging clients. The real-time modules exchange data with each other by means of a virtual data bus, and the real-time modules exchange data with the non-real-time modules by means of a sharing memory.
    Type: Application
    Filed: May 26, 2017
    Publication date: October 17, 2019
    Applicants: NR ELECTRIC CO., LTD, NR ENGINEERING CO., LTD
    Inventors: Hongjun CHEN, Qiang ZHOU, Jifeng WEN, Jiuhu LI, Dongfang XU, Guanghua LI, Wei LIU, Dewen LI, Lei ZHOU, Tianen ZHAO
  • Publication number: 20190190315
    Abstract: An apparatus and method for ensuring the reliability of a protection trip of an intelligent substation. The apparatus comprises a main CPU and an auxiliary CPU connected together, and a main FPGA and an auxiliary FPGA connected together, wherein the main FPGA and the auxiliary FPGA are both connected to a physical layer of a protection apparatus, and the main CPU and the auxiliary CPU are both connected to a state monitoring data output end of a protected device.
    Type: Application
    Filed: April 14, 2016
    Publication date: June 20, 2019
    Applicants: NR ELECTRIC CO., LTD, NR ENGINEERING CO., LTD
    Inventors: Zongguang XU, Jifeng WEN, Yong CHEN, Xiang LI, Yan LI, Yucan ZHAO, Ming YUAN, Qiang ZHOU, Guanghua LI, Tianen ZHAO, Dewen LI
  • Patent number: 9133138
    Abstract: Disclosed is a use of a quinazoline compound of Formula I having 2,4-diaminoquinazoline as a parent nucleus in preparation of a medicament for treating diseases caused by flaviviridae infection, especially a use in combating Hepatitis C virus infection and Dengue fever virus infection.
    Type: Grant
    Filed: December 2, 2011
    Date of Patent: September 15, 2015
    Assignee: SHANGHAI INSTITUTE OF MATERIA MEDICA, CHINESE ACADEMY OF SCIENCES
    Inventors: Jianping Zuo, Youhong Hu, Wei Tang, Bo Chao, Xiankun Tong, Dewen Li, Feihong Ji, Peilan He
  • Publication number: 20130261139
    Abstract: Disclosed is a use of a quinazoline compound of Formula I having 2,4-diaminoquinazoline as a parent nucleus in preparation of a medicament for treating diseases caused by flaviviridae infection, especially a use in combating Hepatitis C virus infection and Dengue fever virus infection.
    Type: Application
    Filed: December 2, 2011
    Publication date: October 3, 2013
    Applicant: SHANGHAI INSTITUTE OF MATERIA MEDICA, CHINESE ACADEMY OF SCIENCES
    Inventors: Jianping Zuo, Youhong Hu, Wei Tang, Bo Chao, Xiankun Tong, Dewen Li, Feihong Ji, Peilan He
  • Publication number: 20110255017
    Abstract: The present invention relates to a on-board TV on railway vehicle that is mounted on a ceiling of a passenger cart, the on-board TV comprises a video display, a triangle support frame and cover plates, where the video display is assembled on the triangular support frame, the cover plates are mounted at two sides of the video display; a mount board is provided in the video display, a circuit board is mounted on one side of the mount board and a display screen is mounted on the other side of the mount board; a power supply/signal input board, an LED control board and a backlight high voltage transformer are provided on the circuit board. The present invention has a simple and reasonable structure, high reliability, an appealing appearance, and practicality; the video display is mounted on the triangular support frame, such that the display inclines downwards a certain angle to satisfy the watching angle of passengers, and meanwhile the video display is compatible and exchangeable.
    Type: Application
    Filed: June 28, 2011
    Publication date: October 20, 2011
    Applicant: QINGDAO SIFANG ROLLING STOCK RESARCH INSTITUTE CO. LTD.
    Inventors: DEWEN LI, CHANGCHANG WANG