Patents by Inventor Dewey Killingsworth

Dewey Killingsworth has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor wafer and method of concurrently testing circuits formed thereon
    Patent number: 9997423
    Abstract: A semiconductor wafer has an array of integrated circuit dies formed on it. Each die is enclosed by a respective seal ring. Each die has a group of bond pads and test pads coupled to the bond pads. A test pad region is formed on the wafer. The test pad region has probe pads and common electrical interconnects that selectively electrically couple each of the probe pads to a bond pad on each of the dies. The common electrical interconnects in the test pad region reduce the possibility of probe damage to the integrated circuits and allow the dies to be tested concurrently before being cut from the wafer.
    Type: Grant
    Filed: May 28, 2014
    Date of Patent: June 12, 2018
    Assignee: NXP USA, INC.
    Inventor: Dewey Killingsworth
  • Semiconductor wafer and method of concurrently testing circuits formed thereon
    Patent number: 9716031
    Abstract: A semiconductor wafer has a non-uniform array of integrated circuit dies formed on it. Each die is enclosed by a respective seal ring, and each die has a group of bond pads and probe pad coupled to the bond pads. Common electrical interconnects selectively electrically couple together respective probe pads of each of the dies. The common electrical interconnects allow the dies to be tested concurrently before being cut from the wafer.
    Type: Grant
    Filed: April 8, 2014
    Date of Patent: July 25, 2017
    Assignee: NXP USA, INC.
    Inventor: Dewey Killingsworth
  • SEMICONDUCTOR WAFER AND METHOD OF CONCURRENTLY TESTING CIRCUITS FORMED THEREON
    Publication number: 20150287656
    Abstract: A semiconductor wafer has an array of integrated circuit dies formed on it. Each die is enclosed by a respective seal ring. Each die has a group of bond pads and test pads coupled to the bond pads. A test pad region is formed on the wafer. The test pad region has probe pads and common electrical interconnects that selectively electrically couple each of the probe pads to a bond pad on each of the dies. The common electrical interconnects in the test pad region reduce the possibility of probe damage to the integrated circuits and allow the dies to be tested concurrently before being cut from the wafer.
    Type: Application
    Filed: May 28, 2014
    Publication date: October 8, 2015
    Applicant: Freescale Semiconductor, Inc.
    Inventor: Dewey Killingsworth
  • SEMICONDUCTOR WAFER AND METHOD OF CONCURRENTLY TESTING CIRCUITS FORMED THEREON
    Publication number: 20150287655
    Abstract: A semiconductor wafer has a non-uniform array of integrated circuit dies formed on it. Each die is enclosed by a respective seal ring, and each die has a group of bond pads and probe pad coupled to the bond pads. Common electrical interconnects selectively electrically couple together respective probe pads of each of the dies. The common electrical interconnects allow the dies to be tested concurrently before being cut from the wafer.
    Type: Application
    Filed: April 8, 2014
    Publication date: October 8, 2015
    Applicant: Freescale Semiconductor, Inc.
    Inventor: Dewey Killingsworth