Patents by Inventor Dexter Elson Semple

Dexter Elson Semple has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Power MOS device with increased channel width and process for forming same
    Patent number: 6677202
    Abstract: A power MOS device that has increased channel width comprises a semiconductor substrate and a doped upper layer of a first conduction type disposed on the substrate. The upper layer comprises a plurality of doped well regions of a second, opposite conduction type and a plurality of heavily doped source regions of the first conduction type at an etched upper surface of the upper layer that comprises parallel corrugations disposed transversely to the source regions. A gate that separates one source region from another comprises an insulating layer and a conductive material. The corrugations provide an increase in width of a channel underlying the gate and the well and source regions.
    Type: Grant
    Filed: January 18, 2001
    Date of Patent: January 13, 2004
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Dexter Elson Semple, Jun Zeng
  • Power MOS device with increased channel width and process for forming same
    Publication number: 20010002327
    Abstract: A power MOS device that has increased channel width comprises a semiconductor substrate and a doped upper layer of a first conduction type disposed on the substrate. The upper layer comprises a plurality of doped well regions of a second, opposite conduction type and a plurality of heavily doped source regions of the first conduction type at an etched upper surface of the upper layer that comprises parallel corrugations disposed transversely to the source regions. A gate that separates one source region from another comprises an insulating layer and a conductive material. The corrugations provide an increase in width of a channel underlying the gate and the well and source regions.
    Type: Application
    Filed: January 18, 2001
    Publication date: May 31, 2001
    Applicant: HARRIS CORPORATION
    Inventors: Dexter Elson Semple, Jun Zeng
  • Power MOS device with increased channel width and process for forming same
    Patent number: 6218701
    Abstract: A power MOS device that has increased channel width comprises a semiconductor substrate and a doped upper layer of a first conduction type disposed on the substrate. The upper layer comprises a plurality of doped well regions of a second, opposite conduction type and a plurality of heavily doped source regions of the first conduction type at an etched upper surface of the upper layer that comprises parallel corrugations disposed transversely to the source regions. A gate that separates one source region from another comprises an insulating layer and a conductive material. The corrugations provide an increase in width of a channel underlying the gate and the well and source regions.
    Type: Grant
    Filed: April 30, 1999
    Date of Patent: April 17, 2001
    Assignee: Intersil Corporation
    Inventors: Dexter Elson Semple, Jun Zeng