Abstract: A thermoplastic polyurethane precursor that can be used to prepare a polyurethane having a low initial yellowness index, high yellowing resistance, high thermal oxidative aging resistance, high hydrolysis resistance, and low fisheye.

Abstract: A surface of a semiconductor substrate defined with at least one fuse area and at least one bonding pad area. A conductive layer with a thickness of 12 k Å and a protective layer are sequentially formed on the surface of the semiconductor substrate. Then portions of the protective layer and portions of the conductive layer in the fuse area are etched to make the thickness for the remaining conductive layer in the fuse area be approximately 5 k Å. Finally a dielectric layer is formed on the surface of the semiconductor substrate, and portions of the first dielectric layer and portions of the protective layer in the bonding pad area are etched until reaching the top surface of the conductive layer.

Abstract: A memory module stores digital data. The memory module has many memory cells biased by a voltage source. Each memory cell has an access transistor electrically connected to a word line and a bit line for receiving bits from the bit line when the word line turns on the access transistor, a switching circuit electrically connected to the access transistor, and a capacitor electrically connected to the switching circuit. The switching circuit turns on or off according to the bit from the access transistor. The capacitor stores charge supplied by the switching circuit when the switching circuit turns on. The capacitor stores charge supplied by the voltage source when the switching circuit turns off. When the access transistor turns off, the switching circuit or the voltage source provides charge to the capacitor to sustain the voltage level of the capacitor to compensate for charge leakage of the capacitor.

Abstract: A SOI DRAM unit comprising a MOS transistor and an improved SOI substrate having a back-gate control. The SOI substrate includes a first insulating layer, a first semiconductor layer having a first conductivity type, a second insulating layer, and a second semiconductor layer having a first conductivity type formed on a substrate. The MOS transistor includes a gate formed on the second semiconductor layer and a source and drain region, having a second conductivity type, formed on either side of the gate in the second semiconductor layer, wherein the source and the drain electrically connects to a bit line and a capacitor, respectively. A first oxidation region is formed in the first semiconductor layer below the source region and a second oxidation region is formed in the first semiconductor layer below the drain region. Both the first oxidation and second oxidation regions are contiguous with the second insulating layer.

Abstract: A method of fabricating a split gate flash memory cell is provided in the present invention. Firstly, a cap layer is formed on the surface of a silicon base of the semiconductor wafer. The surface of the silicon base is then etched to form at least one shallow trench. The shallow trench comprises a vertical sidewall composed of a protion of the silicon base. Next, an ion implantation process is performed using the cap layer to as a mask in order to form a doped area in both the bottom surface of the shallow trench and the silicon base beneath the cap layer. The doped area functions as a source. A first dielectric layer, floating gate, second dielectric layer, and a control gate are formed, respectively, the width of the floating gate being shorter than the width of the first dielectric layer. Then, a third dielectric layer is formed on the control gate and the cap layer is removed.

Abstract: A method of forming a contact pad on a semiconductor wafer is achieved. A first photoresist layer is formed on the surface of a substrate, expect in a region where the contact pad will be formed. A nitrogen ion implantation is performed on the substrate uncovered by the first photoresist layer, followed by the complete removal of the first photoresist layer. Next, a silicon oxide layer is grown on the substrate, except in the region for the formation of the contact pad. Two adjacent MOS transistors are formed on the silicon oxide layer. A conductive layer is formed on the surface of the substrate to cover the two MOS transistors as well as to fill in the gap between the two MOS transistors. A patterned second photoresist layer is subsequently formed on the surface of the conductive layer to define the patterns of the contact pad.

Abstract: The present invention provides a method of planarization for an inter layer dielectric of an EDRAM. The method comprises defining a periphery circuit region and a memory array area on a semiconductor wafer of the EDRAM, and forming a plurality of MOS transistors and capacitors. As well, both a dielectric layer and a photoresist layer are formed on the semiconductor wafer using the layout patterns of a storage node of thecapacitors as a reverse mask to perform an etching process. Consequently, portions of the photoresist layer in the memory array area are removed while simultaneously etching the dielectric layer in the memory array area by a predetermined depth. Finally, a chemical mechanical polishing process is performed on the dielectric layer to planarize the inter layer dielectric of the EDRAM.

Abstract: The present invention provides a method of making a dynamic random access memory (DRAM) unit. The method begins by providing a silicon-on-insulator substrate (SOI), the SOI substrate comprising a first isolation layer formed on a substrate, and a first silicon layer of a first conductive type formed on the first isolation layer. An oxygen ion implantation process is then performed to form a second isolation layer within the first silicon layer, the second isolation layer dividing the first silicon layer into an upper and a lower layer, or a second and a third silicon layer, respectively. Next, a shallow trench isolation is formed in the second silicon layer, as well as an active area isolated by the shallow trench isolation with the second isolation layer on the second silicon layer. Finally, a metal-oxide-semiconductor field-effect-transistor (MOSFET) is formed in the active area in the second silicon layer.

Abstract: A SOI DRAM unit comprising a MOS transistor and an improved SOI substrate having a back-gate control. The SOI substrate includes a first insulating layer, a first semiconductor layer having a first conductivity type, a second insulating layer, and a second semiconductor layer having a first conductivity type formed on a substrate. The MOS transistor includes a gate formed on the second semiconductor layer and a source and drain region, having a second conductivity type, formed on either side of the gate in the second semiconductor layer, wherein the source and the drain electrically connects to a bit line and a capacitor, respectively. A first oxidation region is formed in the first semiconductor layer below the source region and a second oxidation region is formed in the first semiconductor layer below the drain region. Both the first oxidation and second oxidation regions are contiguous with the second insulating layer.

Abstract: The present invention provides a method of planarization for an inter layer dielectric of an EDRAM. The method comprises defining a periphery circuit region and a memory array area on a semiconductor wafer of the EDRAM, and forming a plurality of MOS transistors and capacitors. As well, both a dielectric layer and a photoresist layer are formed on the semiconductor wafer using the layout patterns of a storage node of the capacitors as a reverse mask to perform an etching process. Consequently, portions of the photoresist layer in the memory array area are removed while simultaneously etching the dielectric layer in the memory array area by a predetermined depth. Finally, a chemical mechanical polishing process is performed on the dielectric layer to planarize the inter layer dielectric of the EDRAM.

Abstract: A SOI DRAM unit comprising a MOS transistor and an improved SOI substrate having a back-gate control. The SOI substrate includes a first insulating layer, a first semiconductor layer having a first conductivity type, a second insulating layer, and a second semiconductor layer having a first conductivity type formed on a substrate, respectively. The MOS transistor includes a gate formed on the second semiconductor layer and a source and drain region, having a second conductivity type, formed on either side of the gate in the second semiconductor layer, wherein the source and the drain electrically connects to a bit line and a capacitor, respectively. A first doped region having a second conductivity type is formed in the first semiconductor layer below the source region and a second doped region having a second conductivity type is formed in the first semiconductor layer below the drain region. Both the first doped region and the second doped region are contiguous with the second insulating layer.

Abstract: The present invention provides a method of reducing resistance in an Al-containing conductor. An Al oxide layer is first formed on the surface of an Al-containing conductor followed by the formation of a Ti layer and a barrier layer above the Al oxide layer, respectively. Finally, a W contact plug is formed within the barrier layer. The Al oxide layer functions in preventing a reaction between the Ti layer and the conductor during high temperature formation of the W contact plugs to avoid the influence of resistance in the Al-containing conductor.

Abstract: A method of fabricating a deep trench capacitor is achieved. A deep trench is formed in a silicon substrate followed by the formation of a buried plate in the silicon substrate beneath the deep trench. A silicon nitride layer is formed on the surface of the deep trench above the buried plate. An oxidation process is performed to simultaneously form a first oxide film on the silicon nitride layer and a second oxide film on the silicon substrate within the deep trench. A doped polysilicon layer is formed in the deep trench with its surface lowered down to the surface of the substrate. Finally, a portion of the second oxide film is removed to expose the substrate in the upper region of the deep trench followed by the filling in of an undoped polysilicon layer into the deep trench to finish the fabrication process of the DRAM deep trench capacitor.

Abstract: A method of fabricating a buried vertical split gate memory cell is disclosed. First, a first trench is created in an SOI substrate for accommodating a floating gate. A second trench, having a smaller width than that of the first trench, is then created at the bottom of the first trench for accommodating a word line/control gate. Simultaneously, a silicon sidewall step structure is produced and functions as a vertical channel of the buried vertical split gate memory cell, wherein the vertical control gate channel length (LCG) and the floating gate channel length (LFG) is 0.25 micrometers and about 3.5 nm, respectively.