Abstract: A memory cell includes a storage transistor having the following structure and being dimensioned to shorten program and erase times. A semiconductor body includes a top surface and a trench formed therein having walls joined by a curved bottom. A source zone in the semiconductor body is doped from the top surface. A drain zone in the semiconductor body is doped from the top surface. Junctions of the source and drain zones are beneath each. A gate electrode on the top surface of the semiconductor body is disposed between the source zone and the drain zone in the trench. A dielectric layer isolates the gate electrode from the semiconductor body and acts as a storage medium. Each of the junctions intersects a respective one of the walls at a respective depth from the bottom. A respective spacing across the trench is defined at each depth.

Abstract: The invention relates to a MNOS memory cell arrangement in VLSI (very large scale integration) technology comprised of a multi-layer gate insulating layer covering a surface of a semiconductor body in the region between the source and drain zones. In order to avoid breakdowns at the source and drain zone edges before an erasure voltage is attained, the gate electrode is split into two electrodes, which can be operated in different ways and which are superimposed on upon another. These gate electrodes are connected via self-aligned, overlapped contacts. This arrangement resolves "short channel erasure", even in the case of VLSI technology. The invention can be applied as required to MNOS EEPROM memory devices.