Abstract: In a DC/DC stabilized voltage converting unit having a series circuit including an input filter, a converter stage having a control input and an output filter, the improvement comprising: a control stage having an output connected to the control input; a voltage regulating circuit receptive of an output of the output filter and having an output applied to the control stage; an anti-overvoltage and anti-overcurrent stage receptive of an output of the converter stage and having an output applied to the control stage; a voltage converter chain coupling circuit for effecting the linking of units in a chain; an internal monitoring and commutating circuit connected between the voltage regulating circuit and the control stage for surveying the outputs of the converter stage; a visually and electrically signalling alarm circuit receptive of the outputs of the output filter and having the outputs thereof applied to the chain coupling circuit; and wherein the chain coupling circuit includes a first input for linking to

Abstract: A data processor for a telecommunication system comprises a program and data memory ME controlled by a block MEV including address registers C1, C2, an address store ACT and an instruction counter US, the memory exchanging information with the components of block MEV and with a set of working registers REG via a reading bus l.sub.rl and a writing bus l.sub.w ; another reading bus l.sub.r2 interlinks some of the aforementioned components. An associated execution unit includes an instruction register U divided into two sections MR and UR receiving instruction words from the writing bus, these words consisting of a group of operand bits fed from section UR to a microprogrammed command-signal generator MV and a group of transformation bits fed from section MR to an address store MC.