Abstract: A method of improving synchronization over a secure digital (SD) bus between an SD host and an SD client device is described. The method includes writing to a client event register to interrupt the SD host for an SD extended command. The method also includes triggering the SD host to issue the SD extended command to the SD client device over the SD bus in response to the SD client device writing to the client event register.

Abstract: Various additional and alternative aspects are described herein. In some aspects, the present disclosure provides a method of calibrating a component. The method includes receiving previous calibration parameters for an external component at a secondary SoC from a primary SoC, wherein the secondary SoC is coupled to the external component and configured to calibrate the external component. The method further includes determining validity of the previous calibration parameters by the secondary SoC. The method further includes operating the external component by the secondary SoC based on the determined validity of the previous calibration parameters.

Abstract: A method of improving synchronization over a secure digital (SD) bus between an SD host and an SD client device is described. The method includes writing to a client event register to interrupt the SD host for an SD extended command. The method also includes triggering the SD host to issue the SD extended command to the SD client device over the SD bus in response to the SD client device writing to the client event register.

Abstract: Various aspects include methods for implementing a reduced size firmware storage format on a computing device. Various aspects may include storing a first firmware description table to a first sector of a flash memory, in which the first firmware description table may define a first instance of a firmware including describing a first plurality of firmware images, storing the first plurality of firmware images to a first plurality of consecutive sectors, storing a second firmware description table to a second sector, in which the second firmware description table may define a second instance of the firmware including describing a second plurality of firmware images having a third plurality of firmware images, storing the third plurality of firmware images to a second plurality of consecutive sectors, and booting the computing device using the second firmware description table.

Abstract: Various aspects are described herein. In some aspects, the disclosure provides a method of enabling a multicore framework in a pre-boot environment for a system-on-chip (SoC) comprising a plurality of processors comprising a first processor and a second processor. The method includes initiating, by the first processor, bootup of the SoC into a pre-boot environment. The method further includes scheduling, by the first processor, execution of one or more boot-up tasks by a second processor. The method further includes executing, by the second processor, the one or more boot-up tasks in the pre-boot environment. The method further includes executing, by the first processor, one or more additional tasks in parallel with the second processor executing the one or more boot-up tasks.

Abstract: Various aspects are described herein. In some aspects, the disclosure provides a method for a system-on-chip (SoC) including one or more computing cores. The method includes providing a scheduler to schedule running of threads on the one or more computing cores in a pre-boot environment including a core thread configured to provide a plurality of services. The method further includes providing, by the scheduler, a first lock for the core thread. The method further includes initializing, by the core thread, one or more additional services separate from the plurality of services. The method further includes selectively allowing access to the plurality of services of the core thread to one or more additional threads based on a status of the first lock. The method further includes allowing access to the one or more additional services to the one or more additional threads independent of the status of the first lock.

Abstract: Various additional and alternative aspects are described herein. In some aspects, the present disclosure provides a method of authenticating executable images in a system-on-chip (SoC), the method comprising: storing a plurality of executable images; storing, as separate from the plurality of executable images, a signed image of hashes comprising a plurality of hashes corresponding to the plurality of executable images and a first signature; authenticating the signed image of hashes based on the first signature; and using a first hash of the plurality of hashes to authenticate a first executable image of the plurality of executable images when the signed image of hashes passes authentication.

Abstract: Various additional and alternative aspects are described herein. In some aspects, the present disclosure provides a method of calibrating a component. The method includes receiving previous calibration parameters for an external component at a secondary SoC from a primary SoC, wherein the secondary SoC is coupled to the external component and configured to calibrate the external component. The method further includes determining validity of the previous calibration parameters by the secondary SoC. The method further includes operating the external component by the secondary SoC based on the determined validity of the previous calibration parameters.

Abstract: Various additional and alternative aspects are described herein. In some aspects, the present disclosure provides a method of calibrating a component. The method includes receiving previous calibration parameters for an external component at a secondary SoC from a primary SoC, wherein the secondary SoC is coupled to the external component and configured to calibrate the external component. The method further includes determining validity of the previous calibration parameters by the secondary SoC. The method further includes operating the external component by the secondary SoC based on the determined validity of the previous calibration parameters.

Abstract: Various additional and alternative aspects are described herein. In some aspects, the present disclosure provides a method of operating a system-on-chip (SoC). The method includes selecting a CPU core of a plurality of CPU cores of the SoC to boot the SoC based on information indicative of the quality of the plurality of CPU cores stored on the SoC. The method includes running boot code on the selected CPU.

Abstract: Systems and methods are disclosed for providing stack overflow protection on a system on chip via a hardware write-once register. An exemplary embodiment of an system on chip comprises a hardware write-once register, a boot processor, and one or more processor subsystems. The boot processor is configured to execute a read only memory (ROM) image which initializes the hardware write-once register with a first numeric value in response to the system on chip being powered on. The one or more processor subsystems have an associated software image configured to use the first numeric value in the hardware write-once register as a stack canary value to combat stack overflow attacks.

Abstract: Various aspects are described herein. In some aspects, the disclosure provides a method for a system-on-chip (SoC) including one or more computing cores. The method includes providing a scheduler to schedule running of threads on the one or more computing cores in a pre-boot environment including a core thread configured to provide a plurality of services. The method further includes providing, by the scheduler, a first lock for the core thread. The method further includes initializing, by the core thread, one or more additional services separate from the plurality of services. The method further includes selectively allowing access to the plurality of services of the core thread to one or more additional threads based on a status of the first lock. The method further includes allowing access to the one or more additional services to the one or more additional threads independent of the status of the first lock.

Abstract: Various aspects include methods for implementing a firmware patch infrastructure. Various aspects may include identifying a patchable object from a firmware source code image based on a symbol in the patchable object's name, generating a patchable firmware source code file by injecting a first call to the patchable object configured to call to an indirection table and a second call to the patchable object configure to execute the patchable object, building a patchable firmware source code image from a plurality of patchable firmware source code files including the patchable firmware source code file having the first call to the patchable object and the second call to the patchable object, and creating the indirection table including an entry for the first call from the patchable firmware source code image having an indication to implement the second call in the patchable firmware source code image.

Abstract: Various aspects are described herein. In some aspects, the disclosure provides a method of enabling a multicore framework in a pre-boot environment for a system-on-chip (SoC) comprising a plurality of processors comprising a first processor and a second processor. The method includes initiating, by the first processor, bootup of the SoC into a pre-boot environment. The method further includes scheduling, by the first processor, execution of one or more boot-up tasks by a second processor. The method further includes executing, by the second processor, the one or more boot-up tasks in the pre-boot environment. The method further includes executing, by the first processor, one or more additional tasks in parallel with the second processor executing the one or more boot-up tasks.

Abstract: Systems and methods are disclosed for providing stack overflow protection on a system on chip via a hardware write-once register. An exemplary embodiment of an system on chip comprises a hardware write-once register, a boot processor, and one or more processor subsystems. The boot processor is configured to execute a read only memory (ROM) image which initializes the hardware write-once register with a first numeric value in response to the system on chip being powered on. The one or more processor subsystems have an associated software image configured to use the first numeric value in the hardware write-once register as a stack canary value to combat stack overflow attacks.

Abstract: Techniques for the secure loading of dynamic paged segments are provided. An example method according to the disclosure includes determining a first hash value for each of one or more pageable segments associated with a device, authenticating the one or more pageable segments based on the first hash values, determining a second hash value for each of the one or more pageable segments, transferring the second hash values for each of the pageable segments to the device, determining a load hash value for a loading pageable segment when the loading pageable segment is to be loaded into the device, comparing the load hash value with the second hash value associated with the loading pageable segment, and loading the loading pageable segment in the device when the load hash value matches the second hash value associated with the loading pageable segment.

Abstract: Various aspects include methods for implementing a reduced size firmware storage format on a computing device. Various aspects may include storing a first firmware description table to a first sector of a flash memory, in which the first firmware description table may define a first instance of a firmware including describing a first plurality of firmware images, storing the first plurality of firmware images to a first plurality of consecutive sectors, storing a second firmware description table to a second sector, in which the second firmware description table may define a second instance of the firmware including describing a second plurality of firmware images having a third plurality of firmware images, storing the third plurality of firmware images to a second plurality of consecutive sectors, and booting the computing device using the second firmware description table.

Abstract: Systems, methods, and computer programs are disclosed for providing patchable read only memory (ROM) firmware. One method comprises receiving source code to be used as input for building a read only memory (ROM) image stored on a system on chip (SoC). One or more of a plurality of ROM functions in the source code to be made patchable are identified. The source code for the one or more of the plurality of ROM functions to be made patchable is modified by generating and inserting patching code into the corresponding source code. The patching code comprises a link to a fixed location in random access memory (RAM) for calling the corresponding function.

Abstract: A system and a method for power mode selection in a portable computing device is provided herein. The system and method may comprise operations for operating the portable computing device in a normal mode. The normal mode may utilize a plurality of memory banks within a volatile memory, such as a random access memory (“RAM”), where the memory banks are powered-up and operable to store data. The system and method may further identify a memory segment within the plurality of memory banks, store the memory segment as a stored memory segment (where the stored memory segment is operable to restore the memory segment), and power down the powered-up memory bank associated with the memory segment. Further aspects are described herein.

Abstract: Systems, methods, and computer programs are disclosed for securely booting a system on chip. One embodiment is a system comprising a system on chip (SoC) and a virtual collated internal memory pool (VCIMP). The SoC comprises a bootable processing device having a first internal memory, a read only memory (ROM), and one or more bootable processing subsystems each having a dedicated internal memory. The bootable processing device is configured to execute a bootloader in the ROM. The VCIMP provides time-shared control and access to the one or more bootable processing subsystems during execution of a boot sequence. The VCIMP comprises a contiguous logical-to-physical address mapping of the first internal memory residing on the bootable processing device and the dedicated internal memories residing on the corresponding one or more bootable processing subsystems.