Patents by Inventor Dhananjay Brahme

Dhananjay Brahme has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8316121
    Abstract: A method for arranging a plurality of nodes in a cluster is disclosed. The invention proposes a scheme for creation of a cluster having optimum number of connections and with a diameter of two, meaning any two nodes are at most two edges away from each other. The present invention uses Singer Difference Set for deriving networks with a smaller number of connections per node for clusters of the same size. Further, the method envisaged by the present invention allows multiple computers to be placed at each node with the computers sharing the network in a non-conflicting manner, resulting in a powerful cluster at reduced cost.
    Type: Grant
    Filed: March 11, 2011
    Date of Patent: November 20, 2012
    Assignee: Computational Research Laboratories Limited
    Inventor: Dhananjay Brahme
  • Publication number: 20110161481
    Abstract: A method for arranging a plurality of nodes in a cluster is disclosed. The invention proposes a scheme for creation of a cluster having optimum number of connections and with a diameter of two, meaning any two nodes are at most two edges away from each other. The present invention uses Singer Difference Set for deriving networks with a smaller number of connections per node for clusters of the same size. Further, the method envisaged by the present invention allows multiple computers to be placed at each node with the computers sharing the network in a non-conflicting manner, resulting in a powerful cluster at reduced cost.
    Type: Application
    Filed: March 11, 2011
    Publication date: June 30, 2011
    Inventor: Dhananjay Brahme
  • Publication number: 20060095879
    Abstract: Methods and apparatuses to estimate delay for logic circuit optimization using back annotated placement and delay data. In one aspect of the invention, a method to design a logic circuit, the method includes: modifying a first path that is back annotated with first placement information and first delay information to generate a second path; and calculating a signal delay on the second path from second placement information for the second path, the first placement information and the first delay information (or, computing an adjustment to the first delay information from second placement information for the second path and the first placement information). In one example according to this aspect, the first placement information and the first delay information are back annotated from a timing analysis based on placing and routing at least the first path. An actual route is determined from the first placement information in calculating the signal delay.
    Type: Application
    Filed: December 1, 2005
    Publication date: May 4, 2006
    Inventors: Dhananjay Brahme, Jovanka Ciric, Kenneth McElvain