Patents by Inventor Dhananjay M. Bhusari

Dhananjay M. Bhusari has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230335653
    Abstract: A method for fabricating an upright photovoltaic cell comprises growing one or more epitaxial layers on a substrate, thereby forming a diffused active junction on the substrate and one more additional active junctions above the diffused active junction. The method further comprises selectively etching an areal region of the one or more epitaxial layers, thereby forming a mesa on the substrate and exposing a substrate-contact region parallel to the areal region at a base of the mesa. The method further comprises depositing contact material onto the substrate-contact region, to form the first contact, and concertedly onto a mesa-contact region of the mesa, to form the second contact.
    Type: Application
    Filed: September 29, 2021
    Publication date: October 19, 2023
    Inventors: Philip T. Chiu, Dhananjay M. Bhusari, Richard Thai
  • Patent number: 9564548
    Abstract: The disclosure provides for a direct wafer bonding method including providing a bonding layer upon a first and second wafer, and directly bonding the first and second wafers together under heat and pressure. The method may be used for directly bonding an GaAs-based, InP-based, GaP-based, GaSb-based, or Ga(In)N-based device to a GaAs device by introducing a highly doped (Al)(Ga)InP(As)(Sb) layer between the devices. The bonding layer material forms a bond having high bond strength, low electrical resistance, and high optical transmittance.
    Type: Grant
    Filed: August 18, 2014
    Date of Patent: February 7, 2017
    Assignee: The Boeing Company
    Inventors: Dhananjay M. Bhusari, Daniel C. Law
  • Publication number: 20140352787
    Abstract: The disclosure provides for a direct wafer bonding method including providing a bonding layer upon a first and second wafer, and directly bonding the first and second wafers together under heat and pressure. The method may be used for directly bonding an GaAs-based, InP-based, GaP-based, GaSb-based, or Ga(In)N-based device to a GaAs device by introducing a highly doped (Al)(Ga)InP(As)(Sb) layer between the devices. The bonding layer material forms a bond having high bond strength, low electrical resistance, and high optical transmittance.
    Type: Application
    Filed: August 18, 2014
    Publication date: December 4, 2014
    Inventors: Dhananjay M. Bhusari, Daniel C. Law
  • Patent number: 8822817
    Abstract: The disclosure provides for a direct wafer bonding method including providing a bonding layer upon a first and second wafer, and directly bonding the first and second wafers together under heat and pressure. The method may be used for directly bonding an GaAs-based, InP-based, GaP-based, GaSb-based, or Ga(In)N-based device to a GaAs device by introducing a highly doped (Al)(Ga)InP(As)(Sb) layer between the devices. The bonding layer material forms a bond having high bond strength, low electrical resistance, and high optical transmittance.
    Type: Grant
    Filed: December 3, 2010
    Date of Patent: September 2, 2014
    Assignee: The Boeing Company
    Inventors: Dhananjay M. Bhusari, Daniel C. Law
  • Publication number: 20120138116
    Abstract: The disclosure provides for a direct wafer bonding method including providing a bonding layer upon a first and second wafer, and directly bonding the first and second wafers together under heat and pressure. The method may be used for directly bonding an GaAs-based, InP-based, GaP-based, GaSb-based, or Ga(In)N-based device to a GaAs device by introducing a highly doped (Al)(Ga)InP(As)(Sb) layer between the devices. The bonding layer material forms a bond having high bond strength, low electrical resistance, and high optical transmittance.
    Type: Application
    Filed: December 3, 2010
    Publication date: June 7, 2012
    Applicant: THE BOEING COMPANY
    Inventors: Dhananjay M. BHUSARI, Daniel C. LAW
  • Patent number: 6888249
    Abstract: A method of forming an air gap or gaps within solid structures and specifically semiconductor structures to reduce capacitive coupling between electrical elements such as metal lines, wherein a sacrificial material is used to occupy a closed interior volume in a semiconductor structure is disclosed. The sacrificial material is caused to decompose into one or more gaseous decomposition products which are removed, in one embodiment by diffusion, through an overcoat layer. The decomposition of the sacrificial material leaves an air gap or gaps at the closed interior volume previously occupied by the sacrificial material. The air gaps may be disposed between electrical leads to minimize capacitive coupling therebetween. Also disclosed are methods of forming multi-level air gaps and methods or forming over-coated conductive lines or leads wherein a portion of the overcoating is in contact with at least one air gap.
    Type: Grant
    Filed: August 25, 2003
    Date of Patent: May 3, 2005
    Assignee: Georgia Tech Research Corporation
    Inventors: Paul Albert Kohl, Sue Ann Bidstrup Allen, Clifford Lee Henderson, Hollie Ann Reed, Dhananjay M. Bhusari
  • Publication number: 20040038513
    Abstract: A method of forming an air gap or gaps within solid structures and specifically semiconductor structures to reduce capacitive coupling between electrical elements such as metal lines, wherein a sacrificial material is used to occupy a closed interior volume in a semiconductor structure is disclosed. The sacrificial material is caused to decompose into one or more gaseous decomposition products which are removed, in one embodiment by diffusion, through an overcoat layer. The decomposition of the sacrificial material leaves an air gap or gaps at the closed interior volume previously occupied by the sacrificial material. The air gaps may be disposed between electrical leads to minimize capacitive coupling therebetween.
    Type: Application
    Filed: August 25, 2003
    Publication date: February 26, 2004
    Inventors: Paul Albert Kohl, Sue Ann Bidstrup Allen, Clifford Lee Henderson, Hollie Ann Reed, Dhananjay M. Bhusari
  • Patent number: 6610593
    Abstract: A method of forming an air gap or gaps within solid structures and specifically semiconductor structures to reduce capacitive coupling between electrical elements such as metal lines, wherein a sacrificial material is used to occupy a closed interior volume in a semiconductor structure is disclosed. The sacrificial material is caused to decompose into one or more gaseous decomposition products which are removed, in one embodiment by diffusion, through an overcoat layer. The decomposition of the sacrificial material leaves an air gap or gaps at the closed interior volume previously occupied by the sacrificial material. The air gaps may be disposed between electrical leads to minimize capacitive coupling therebetween. Also disclosed are methods of forming multi-level air gaps and methods or forming over-coated conductive lines or leads wherein a portion of the overcoating is in contact with at least one air gap.
    Type: Grant
    Filed: August 31, 2001
    Date of Patent: August 26, 2003
    Assignee: Georgia Tech Research Corporation
    Inventors: Paul Albert Kohl, Sue Ann Bidstrup Allen, Clifford Lee Henderson, Hollie Anne Reed, Dhananjay M. Bhusari
  • Publication number: 20020081787
    Abstract: A method of forming an air gap or gaps within solid structures and specifically semiconductor structures to reduce capacitive coupling between electrical elements such as metal lines, wherein a sacrificial material is used to occupy a closed interior volume in a semiconductor structure is disclosed. The sacrificial material is caused to decompose into one or more gaseous decomposition products which are removed, in one embodiment by diffusion, through an overcoat layer. The decomposition of the sacrificial material leaves an air gap or gaps at the closed interior volume previously occupied by the sacrificial material. The air gaps may be disposed between electrical leads to minimize capacitive coupling therebetween.
    Type: Application
    Filed: August 31, 2001
    Publication date: June 27, 2002
    Inventors: Paul Albert Kohl, Sue Ann Bldstrup Allen, Clifford Lee Henderson, Hollie Anne Reed, Dhananjay M. Bhusari