Patents by Inventor Dhananjay S. Brahme

Dhananjay S. Brahme has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus to estimate delay for logic circuit optimization
    Patent number: 7434187
    Abstract: Methods and apparatuses to estimate delay for logic circuit optimization using back annotated placement and delay data. In one aspect of the invention, a method to design a logic circuit, the method includes: modifying a first path that is back annotated with first placement information and first delay information to generate a second path; and calculating a signal delay on the second path from second placement information for the second path, the first placement information and the first delay information (or, computing an adjustment to the first delay information from second placement information for the second path and the first placement information). In one example according to this aspect, the first placement information and the first delay information are back annotated from a timing analysis based on placing and routing at least the first path. An actual route is determined from the first placement information in calculating the signal delay.
    Type: Grant
    Filed: December 1, 2005
    Date of Patent: October 7, 2008
    Assignee: Synopsys, Inc.
    Inventors: Dhananjay S. Brahme, Jovanka Ciric, Kenneth S. McElvain
  • Method and apparatus to estimate delay for logic circuit optimization
    Patent number: 6973632
    Abstract: Methods and apparatuses to estimate delay for logic circuit optimization using back annotated placement and delay data. In one aspect of the invention, a method to design a logic circuit, the method includes: modifying a first path that is back annotated with first placement information and first delay information to generate a second path; and calculating a signal delay on the second path from second placement information for the second path, the first placement information and the first delay information (or, computing an adjustment to the first delay information from second placement information for the second path and the first placement information). In one example according to this aspect, the first placement information and the first delay information are back annotated from a timing analysis based on placing and routing at least the first path. An actual route is determined from the first placement information in calculating the signal delay.
    Type: Grant
    Filed: December 4, 2002
    Date of Patent: December 6, 2005
    Assignee: Synplicity, Inc.
    Inventors: Dhananjay S. Brahme, Jovanka Ciric, Kenneth S. McElvain