Abstract: A method and structure that forms a PCB while removing or eliminating a stub from a via without back-drilling or doing multi-laminations. In the preferred embodiment, the printed circuit board includes a via extending through a plurality of stacked layers. The via includes a plated through hole that is connected to at least two other metalized layers. There is a portion of the via that is extraneous and that has a negative performance on the functionality of the printed circuit board. The single lamination buried via method adds a seed layer resist that prevents an electrical connection during electroplating thus preventing the via from metalizing where it is not desired.

Abstract: The present invention provides for a method and structure for forming three-dimensionally routed dielectric wires between discrete points on the two or more parallel circuit planes. The wires may be freely routed in three-dimensional space as to create the most efficient routing between the two arbitrarily defined points on the two or more parallel circuit planes. Metalizing the outer surfaces of these three dimensional dielectric wires electrically coupling the discrete wires to their respective discrete contact points. Two or more of these wires may be in intimate contact to one another electrically coupling to each other as well as to two or more discrete contact pads. These electrically coupled contact pads may be on opposite sides or on the same side of the structure and the formed metalized wires may originate on one side and terminate on the other or originate and terminate from the same side.

Abstract: The present invention describes essentially three different embodiments for the implementation of low impedance (over frequency) power delivery to a die. Such low impedance to a high frequency allows the die to operate at package-level speed, thus reducing yield loss at the packaging level. Each embodiment addresses a slightly different aspect of the overall wafer probe application. In each embodiment, however, the critical improvement of this disclosure is the location of the passive components used for supply filtering/decoupling relative to prior art. All three embodiments require a method to embed the passive components in close proximity to the pitch translation substrate or physically in the pitch translation substrate.

Abstract: The present invention describes essentially three different embodiments for the implementation of low impedance (over frequency) power delivery to a die. Such low impedance to a high frequency allows the die to operate at package-level speed, thus reducing yield loss at the packaging level. Each embodiment addresses a slightly different aspect of the overall wafer probe application. In each embodiment, however, the critical improvement of this disclosure is the location of the passive components used for supply filtering/decoupling relative to prior art. All three embodiments require a method to embed the passive components in close proximity to the pitch translation substrate or physically in the pitch translation substrate.

Abstract: A method and electrical interconnect structure internal to a printed circuit board for the purposes of creating a reliable, high performing connection method between embedded component terminals, signal traces and or power/ground planes which may occupy the same vertical space as the embedded components, such as a capacitor or resistor. Further easing the assembly and reliability through the manufacturing process of said embedded component structures. In one structure castellated drilled, plated vias connect the trace or plane within the printed circuit board to the electrical terminals of the embedded component using a permanent and highly conductive attach material. In another structure, the trace or plane connect by selective side-wall plating, which surrounds the electrical terminal of the component.