Patents by Inventor Dhananjayan Athiyappan

Dhananjayan Athiyappan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250077126
    Abstract: A processing device in a memory sub-system identifies an indication of a completion of a memory access command directed to a memory device and determines whether there are other memory access commands directed to the memory device that are pending. Responsive to determining that there are other memory access commands pending, the processing device coalesces additional indications of completions of the other memory access commands that are available within a threshold period of time with the indication of the completion into a completion data chunk and sends the completion data chunk to a host system. The host system is to store the completion data chunk as one or more completion queue entries in a completion queue in a host memory of the host system via a single host memory write operation.
    Type: Application
    Filed: November 18, 2024
    Publication date: March 6, 2025
    Inventors: Sahil Soi, Dhananjayan Athiyappan
  • Patent number: 12182445
    Abstract: A processing device in a memory sub-system identifies an indication of a completion of a memory access command directed to a memory device and determines whether there are other memory access commands directed to the memory device that are pending. Responsive to determining that there are other memory access commands pending, the processing device coalesces additional indications of completions of the other memory access commands that are available within a threshold period of time with the indication of the completion into a completion data chunk and sends the completion data chunk to a host system. The host system is to store the completion data chunk as one or more completion queue entries in a completion queue in a host memory of the host system via a single host memory write operation.
    Type: Grant
    Filed: August 11, 2022
    Date of Patent: December 31, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Sahil Soi, Dhananjayan Athiyappan
  • Publication number: 20240348437
    Abstract: Various embodiments include methods implemented in a processor for management of cryptographic keys of an integrated cryptographic engine. Embodiments may include detecting a cryptographic key access control event, determining whether the cryptographic key access control event is for disabling cryptographic key access at a cryptographic key memory of the integrated cryptographic engine, disabling cryptographic key access at the cryptographic key memory in response to determining that the cryptographic key access control event is for disabling cryptographic key access at the cryptographic key memory, and maintaining one or more cryptographic keys at the cryptographic key memory for which cryptographic key access is disabled. Embodiments may further include enabling cryptographic key access at the cryptographic key memory in response to determining that the cryptographic key access control event is not for disabling cryptographic key access at the cryptographic key memory.
    Type: Application
    Filed: April 17, 2023
    Publication date: October 17, 2024
    Inventors: Sridhar ANUMALA, Bharani BHUVANAGIRI, Nishanth KUMAR, Dhananjayan ATHIYAPPAN, Madhu Yashwanth BOENAPALLI
  • Publication number: 20230214157
    Abstract: A processing device in a memory sub-system identifies an indication of a completion of a memory access command directed to a memory device and determines whether there are other memory access commands directed to the memory device that are pending. Responsive to determining that there are other memory access commands pending, the processing device coalesces additional indications of completions of the other memory access commands that are available within a threshold period of time with the indication of the completion into a completion data chunk and sends the completion data chunk to a host system. The host system is to store the completion data chunk as one or more completion queue entries in a completion queue in a host memory of the host system via a single host memory write operation.
    Type: Application
    Filed: August 11, 2022
    Publication date: July 6, 2023
    Inventors: Sahil Soi, Dhananjayan Athiyappan