Abstract: The techniques described herein provide an instruction fetch and decode unit having an operation cache with low latency in switching between fetching decoded operations from the operation cache and fetching and decoding instructions using a decode unit. This low latency is accomplished through a synchronization mechanism that allows work to flow through both the operation cache path and the instruction cache path until that work is stopped due to needing to wait on output from the opposite path. The existence of decoupling buffers in the operation cache path and the instruction cache path allows work to be held until that work is cleared to proceed. Other improvements, such as a specially configured operation cache tag array that allows for detection of multiple hits in a single cycle, also improve latency by, for example, improving the speed at which entries are consumed from a prediction queue that stores predicted address blocks.

Abstract: The techniques described herein provide an instruction fetch and decode unit having an operation cache with low latency in switching between fetching decoded operations from the operation cache and fetching and decoding instructions using a decode unit. This low latency is accomplished through a synchronization mechanism that allows work to flow through both the operation cache path and the instruction cache path until that work is stopped due to needing to wait on output from the opposite path. The existence of decoupling buffers in the operation cache path and the instruction cache path allows work to be held until that work is cleared to proceed. Other improvements, such as a specially configured operation cache tag array that allows for detection of multiple hits in a single cycle, also improve latency by, for example, improving the speed at which entries are consumed from a prediction queue that stores predicted address blocks.

Abstract: A data compressor for a lossless data compression system includes a hardware aware encoder and a key signal processor. The hardware aware encoder encodes a data value signal into a key signal according to a key assignment formed by determining a number of data values of a value space in which each data value comprises a plurality of bits, determining a size of the key to encode the number of data values of the value space, grouping the data values into a plurality of groups based on a fewest number of bit differences between data values in each group, and assigning fragments of the key based on a fewest number of bits that can differentiate groups based on remaining bits of the data values. The key signal processor has an output adapted to be coupled to a medium for providing a representation of the key signal to the output.