Patents by Inventor Dhani Reddy Sreenivasula Reddy
Dhani Reddy Sreenivasula Reddy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10783956Abstract: An apparatus and method are provided for implementing write assist with boost attenuation for static random access memory (SRAM) arrays. The apparatus includes a memory array comprising a plurality of SRAM cells. The apparatus further includes a write driver connected to each of a differential pair of bit lines in each of the plurality of SRAM cells of the memory array. The apparatus further includes a write assist attenuation circuit connected to the write driver, the write assist attenuation circuit comprising a clamping device configured to modify a control signal as a function of supply voltage and process to attenuate an amount of boost applied to pull one of the bit lines below ground in an active phase of a write cycle.Type: GrantFiled: January 9, 2019Date of Patent: September 22, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dinesh Chandra, Eswararao Potladhurthi, Dhani Reddy Sreenivasula Reddy, Krishnan S. Rengarajan
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Patent number: 10783958Abstract: An apparatus and method are provided for implementing write assist with boost attenuation for static random access memory (SRAM) arrays. The apparatus includes a memory array comprising a plurality of SRAM cells. The apparatus further includes a write driver connected to each of a differential pair of bit lines in each of the plurality of SRAM cells of the memory array. The apparatus further includes a write assist attenuation circuit connected to the write driver, the write assist attenuation circuit comprising a clamping device configured to modify a control signal as a function of supply voltage and process to attenuate an amount of boost applied to pull one of the bit lines below ground in an active phase of a write cycle.Type: GrantFiled: April 19, 2019Date of Patent: September 22, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dinesh Chandra, Eswararao Potladhurthi, Dhani Reddy Sreenivasula Reddy, Krishnan S. Rengarajan
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Patent number: 10672439Abstract: The present disclosure relates to a structure which includes at least one keeper circuit which is configured to hold data to a precharged state during a first operation and be disabled during a second operation.Type: GrantFiled: July 10, 2018Date of Patent: June 2, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Dhani Reddy Sreenivasula Reddy, Md Nadeem Iqbal
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Publication number: 20200020370Abstract: The present disclosure relates to a structure which includes at least one keeper circuit which is configured to hold data to a precharged state during a first operation and be disabled during a second operation.Type: ApplicationFiled: July 10, 2018Publication date: January 16, 2020Inventors: Dhani Reddy SREENIVASULA REDDY, Md Nadeem IQBAL
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Publication number: 20190304536Abstract: An apparatus and method are provided for implementing write assist with boost attenuation for static random access memory (SRAM) arrays. The apparatus includes a memory array comprising a plurality of SRAM cells. The apparatus further includes a write driver connected to each of a differential pair of bit lines in each of the plurality of SRAM cells of the memory array. The apparatus further includes a write assist attenuation circuit connected to the write driver, the write assist attenuation circuit comprising a clamping device configured to modify a control signal as a function of supply voltage and process to attenuate an amount of boost applied to pull one of the bit lines below ground in an active phase of a write cycle.Type: ApplicationFiled: April 19, 2019Publication date: October 3, 2019Inventors: Dinesh CHANDRA, Eswararao POTLADHURTHI, Dhani Reddy Sreenivasula REDDY, Krishnan S. RENGARAJAN
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Publication number: 20190267053Abstract: The present disclosure relates to a structure which includes an assist circuit which is configured to add a boost voltage using a common boost logic device for both a read logic circuit and a write logic circuit of the assist circuit.Type: ApplicationFiled: February 27, 2018Publication date: August 29, 2019Inventors: Dhani Reddy SREENIVASULA REDDY, Vinay BHAT SOORI
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Patent number: 10381054Abstract: The present disclosure relates to a structure which includes an assist circuit which is configured to add a boost voltage using a common boost logic device for both a read logic circuit and a write logic circuit of the assist circuit.Type: GrantFiled: February 27, 2018Date of Patent: August 13, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Dhani Reddy Sreenivasula Reddy, Vinay Bhat Soori
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Patent number: 10319431Abstract: An apparatus and method are provided for implementing write assist with boost attenuation for static random access memory (SRAM) arrays. The apparatus includes a memory array comprising a plurality of SRAM cells. The apparatus further includes a write driver connected to each of a differential pair of bit lines in each of the plurality of SRAM cells of the memory array. The apparatus further includes a write assist attenuation circuit connected to the write driver, the write assist attenuation circuit comprising a clamping device configured to modify a control signal as a function of supply voltage and process to attenuate an amount of boost applied to pull one of the bit lines below ground in an active phase of a write cycle.Type: GrantFiled: October 31, 2017Date of Patent: June 11, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dinesh Chandra, Eswararao Potladhurthi, Dhani Reddy Sreenivasula Reddy, Krishnan S. Rengarajan
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Publication number: 20190147946Abstract: An apparatus and method are provided for implementing write assist with boost attenuation for static random access memory (SRAM) arrays. The apparatus includes a memory array comprising a plurality of SRAM cells. The apparatus further includes a write driver connected to each of a differential pair of bit lines in each of the plurality of SRAM cells of the memory array. The apparatus further includes a write assist attenuation circuit connected to the write driver, the write assist attenuation circuit comprising a clamping device configured to modify a control signal as a function of supply voltage and process to attenuate an amount of boost applied to pull one of the bit lines below ground in an active phase of a write cycle.Type: ApplicationFiled: January 9, 2019Publication date: May 16, 2019Inventors: Dinesh CHANDRA, Eswararao POTLADHURTHI, Dhani Reddy Sreenivasula REDDY, Krishnan S. RENGARAJAN
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Patent number: 10217510Abstract: An apparatus and method are provided for implementing write assist with boost attenuation for static random access memory (SRAM) arrays. The apparatus includes a memory array comprising a plurality of SRAM cells. The apparatus further includes a write driver connected to each of a differential pair of bit lines in each of the plurality of SRAM cells of the memory array. The apparatus further includes a write assist attenuation circuit connected to the write driver, the write assist attenuation circuit comprising a clamping device configured to modify a control signal as a function of supply voltage and process to attenuate an amount of boost applied to pull one of the bit lines below ground in an active phase of a write cycle.Type: GrantFiled: October 31, 2017Date of Patent: February 26, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dinesh Chandra, Eswararao Potladhurthi, Dhani Reddy Sreenivasula Reddy, Krishnan S. Rengarajan
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Patent number: 10199095Abstract: A structure includes a write bit switch device which includes a plurality of bit switch devices positioned at different positions of a memory cell array, and which is configured to enable write operations at a specified number of cells per bit line using a strapped bit line on a selected column of the memory cell array.Type: GrantFiled: September 1, 2017Date of Patent: February 5, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Dhani Reddy Sreenivasula Reddy, Venkatraghavan Bringivijayaraghavan, Vinay Bhat Soori
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Patent number: 9984742Abstract: An apparatus and method are provided for implementing write assist with boost attenuation for static random access memory (SRAM) arrays. The apparatus includes a memory array comprising a plurality of SRAM cells. The apparatus further includes a write driver connected to each of a differential pair of bit lines in each of the plurality of SRAM cells of the memory array. The apparatus further includes a write assist attenuation circuit connected to the write driver, the write assist attenuation circuit comprising a clamping device configured to modify a control signal as a function of supply voltage and process to attenuate an amount of boost applied to pull one of the bit lines below ground in an active phase of a write cycle.Type: GrantFiled: April 13, 2016Date of Patent: May 29, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dinesh Chandra, Eswararao Potladhurthi, Dhani Reddy Sreenivasula Reddy, Krishnan S. Rengarajan
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Publication number: 20180130522Abstract: An apparatus and method are provided for implementing write assist with boost attenuation for static random access memory (SRAM) arrays. The apparatus includes a memory array comprising a plurality of SRAM cells. The apparatus further includes a write driver connected to each of a differential pair of bit lines in each of the plurality of SRAM cells of the memory array. The apparatus further includes a write assist attenuation circuit connected to the write driver, the write assist attenuation circuit comprising a clamping device configured to modify a control signal as a function of supply voltage and process to attenuate an amount of boost applied to pull one of the bit lines below ground in an active phase of a write cycle.Type: ApplicationFiled: October 31, 2017Publication date: May 10, 2018Inventors: Dinesh CHANDRA, Eswararao POTLADHURTHI, Dhani Reddy Sreenivasula REDDY, Krishnan S. RENGARAJAN
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Publication number: 20180068717Abstract: An apparatus and method are provided for implementing write assist with boost attenuation for static random access memory (SRAM) arrays. The apparatus includes a memory array comprising a plurality of SRAM cells. The apparatus further includes a write driver connected to each of a differential pair of bit lines in each of the plurality of SRAM cells of the memory array. The apparatus further includes a write assist attenuation circuit connected to the write driver, the write assist attenuation circuit comprising a clamping device configured to modify a control signal as a function of supply voltage and process to attenuate an amount of boost applied to pull one of the bit lines below ground in an active phase of a write cycle.Type: ApplicationFiled: October 31, 2017Publication date: March 8, 2018Inventors: Dinesh CHANDRA, Eswararao POTLADHURTHI, Dhani Reddy Sreenivasula REDDY, Krishnan S. RENGARAJAN
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Patent number: 9847119Abstract: An apparatus and method are provided for implementing write assist with boost attenuation for static random access memory (SRAM) arrays. The apparatus includes a memory array comprising a plurality of SRAM cells. The apparatus further includes a write driver connected to each of a differential pair of bit lines in each of the plurality of SRAM cells of the memory array. The apparatus further includes a write assist attenuation circuit connected to the write driver, the write assist attenuation circuit comprising a clamping device configured to modify a control signal as a function of supply voltage and process to attenuate an amount of boost applied to pull one of the bit lines below ground in an active phase of a write cycle.Type: GrantFiled: September 15, 2016Date of Patent: December 19, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dinesh Chandra, Eswararao Potladhurthi, Dhani Reddy Sreenivasula Reddy, Krishnan S. Rengarajan
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Publication number: 20170004876Abstract: An apparatus and method are provided for implementing write assist with boost attenuation for static random access memory (SRAM) arrays. The apparatus includes a memory array comprising a plurality of SRAM cells. The apparatus further includes a write driver connected to each of a differential pair of bit lines in each of the plurality of SRAM cells of the memory array. The apparatus further includes a write assist attenuation circuit connected to the write driver, the write assist attenuation circuit comprising a clamping device configured to modify a control signal as a function of supply voltage and process to attenuate an amount of boost applied to pull one of the bit lines below ground in an active phase of a write cycle.Type: ApplicationFiled: September 15, 2016Publication date: January 5, 2017Inventors: Dinesh CHANDRA, Eswararao POTLADHURTHI, Dhani Reddy Sreenivasula REDDY, Krishnan S. RENGARAJAN
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Patent number: 9496025Abstract: An apparatus and method are provided for implementing write assist with boost attenuation for static random access memory (SRAM) arrays. The apparatus includes a memory array comprising a plurality of SRAM cells. The apparatus further includes a write driver connected to each of a differential pair of bit lines in each of the plurality of SRAM cells of the memory array. The apparatus further includes a write assist attenuation circuit connected to the write driver, the write assist attenuation circuit comprising a clamping device configured to modify a control signal as a function of supply voltage and process to attenuate an amount of boost applied to pull one of the bit lines below ground in an active phase of a write cycle.Type: GrantFiled: January 12, 2015Date of Patent: November 15, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dinesh Chandra, Eswararao Potladhurthi, Dhani Reddy Sreenivasula Reddy, Krishnan S. Rengarajan
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Publication number: 20160232966Abstract: An apparatus and method are provided for implementing write assist with boost attenuation for static random access memory (SRAM) arrays. The apparatus includes a memory array comprising a plurality of SRAM cells. The apparatus further includes a write driver connected to each of a differential pair of bit lines in each of the plurality of SRAM cells of the memory array. The apparatus further includes a write assist attenuation circuit connected to the write driver, the write assist attenuation circuit comprising a clamping device configured to modify a control signal as a function of supply voltage and process to attenuate an amount of boost applied to pull one of the bit lines below ground in an active phase of a write cycle.Type: ApplicationFiled: April 13, 2016Publication date: August 11, 2016Inventors: Dinesh CHANDRA, Eswararao POTLADHURTHI, Dhani Reddy Sreenivasula REDDY, Krishnan S. RENGARAJAN
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Publication number: 20160203857Abstract: An apparatus and method are provided for implementing write assist with boost attenuation for static random access memory (SRAM) arrays. The apparatus includes a memory array comprising a plurality of SRAM cells. The apparatus further includes a write driver connected to each of a differential pair of bit lines in each of the plurality of SRAM cells of the memory array. The apparatus further includes a write assist attenuation circuit connected to the write driver, the write assist attenuation circuit comprising a clamping device configured to modify a control signal as a function of supply voltage and process to attenuate an amount of boost applied to pull one of the bit lines below ground in an active phase of a write cycle.Type: ApplicationFiled: January 12, 2015Publication date: July 14, 2016Inventors: Dinesh CHANDRA, Eswararao POTLADHURTHI, Dhani Reddy Sreenivasula REDDY, Krishnan S. RENGARAJAN
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Patent number: 9208859Abstract: A memory circuit configured for reducing dynamic read power is disclosed that includes a first read global bit line connected to a first sense amp and a second read global bit line connected to a second sense amp. The second read global bit line is adjacent to the first read global bit line. The memory circuit further includes a third read global bit line and logic circuitry connected to the first read global bit line, the second read global bit line, and the third read global bit line. The logic circuitry is configured to determine when both the first read global bit line and the second read global bit line are evaluated as in a high state, and in response to the determining, toggle the third read global bit line to the high state.Type: GrantFiled: August 22, 2014Date of Patent: December 8, 2015Assignee: GLOBALFOUNDRIES INC.Inventors: Venkatraghavan Bringivijayaraghavan, Dhani Reddy Sreenivasula Reddy