Patents by Inventor Dhanya K

Dhanya K has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • High-speed frequency divider and a phase locked loop that uses the high-speed frequency divider
    Patent number: 8248118
    Abstract: A frequency divider includes a least significant (LS) stage, multiple cascaded divider stages, and an output stage. The LS stage receives an input signal, a program bit and a first mode signal, and generates a first frequency-divided signal and an output mode signal. Each of the plurality of divider stages divides the frequency of an output of an immediately previous stage by a value specified by a corresponding program bit and a corresponding mode signal. A first divider stage in the plurality of divider stages is coupled to receive the first frequency-divided signal and to generate the first mode signal. The output stage receives the output mode signal and a control signal, and generates an output signal by dividing a frequency of the output mode signal by two if the control signal is at one logic level. The output stage forwards the output mode signal without division otherwise.
    Type: Grant
    Filed: August 9, 2010
    Date of Patent: August 21, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Karthik Subburaj, Dhanya K
  • HIGH-SPEED FREQUENCY DRIVER AND A PHASE LOCKED LOOP THAT USES THE HIGH-SPEED FREQUENCY DIVIDER
    Publication number: 20120194235
    Abstract: A frequency divider includes a least significant (LS) stage, multiple cascaded divider stages, and an output stage. The LS stage receives an input signal, a program bit and a first mode signal, and generates a first frequency-divided signal and an output mode signal. Each of the plurality of divider stages divides the frequency of an output of an immediately previous stage by a value specified by a corresponding program bit and a corresponding mode signal. A first divider stage in the plurality of divider stages is coupled to receive the first frequency-divided signal and to generate the first mode signal. The output stage receives the output mode signal and a control signal, and generates an output signal by dividing a frequency of the output mode signal by two if the control signal is at one logic level. The output stage forwards the output mode signal without division otherwise.
    Type: Application
    Filed: March 20, 2012
    Publication date: August 2, 2012
    Inventors: Karthik Subburaj, Dhanya K
  • HIGH-SPEED FREQUENCY DIVIDER AND A PHASE LOCKED LOOP THAT USES THE HIGH-SPEED FREQUENCY DIVIDER
    Publication number: 20120032715
    Abstract: A frequency divider includes a least significant (LS) stage, multiple cascaded divider stages, and an output stage. The LS stage receives an input signal, a program bit and a first mode signal, and generates a first frequency-divided signal and an output mode signal. Each of the plurality of divider stages divides the frequency of an output of an immediately previous stage by a value specified by a corresponding program bit and a corresponding mode signal. A first divider stage in the plurality of divider stages is coupled to receive the first frequency-divided signal and to generate the first mode signal. The output stage receives the output mode signal and a control signal, and generates an output signal by dividing a frequency of the output mode signal by two if the control signal is at one logic level. The output stage forwards the output mode signal without division otherwise.
    Type: Application
    Filed: August 9, 2010
    Publication date: February 9, 2012
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Karthik Subburaj, Dhanya K