Patents by Inventor Dharam P. Gosain

Dharam P. Gosain has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5637180
    Abstract: A plasma-processing method used in processes for manufacturing semiconductor devices. During plasma processing, ultraviolet radiation is emitted from a region where a plasma is created. An ultraviolet radiation-blocking means blocks the ultraviolet radiation from impinging on the sample surface to protect it. The blocking means passes particles forming a plasma onto the sample surface. The particles passed through the ultraviolet radiation-blocking plates are implanted into the sample. Alternatively, the processed surface of the sample is etched, or a film is deposited on the processed surface of the sample.
    Type: Grant
    Filed: September 25, 1995
    Date of Patent: June 10, 1997
    Assignee: Sony Corporation
    Inventors: Dharam P. Gosain, Jonathan Westwater, Setsuo Usui
  • Patent number: 5627085
    Abstract: The present invention improves a current--voltage characteristic by perfectly eliminating defects in the polycrystal silicon layer of TFT by hydrogenation. In the first process, hydrogen is doped into the polycrystal silicon layer 16 of TFT 1 by the hydrogen plasma doping method to eliminate a greater part of the defects in the polycrystal silicon layer 16. Thereafter, in the second process, after an amorphous silicon nitride film 23 including hydrogen is formed on the polycrystal silicon layer 16 or on the stopper layer 17 provided on the polycrystal silicon layer 16, hydrogen is released from the amorphous silicon nitride film 23 including hydrogen by the annealing process and such released hydrogen is then diffused into the polycrystal silicon layer 16 in order to eliminate remaining defects in the polycrystal silicon layer 16.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: May 6, 1997
    Assignee: Sony Corporation
    Inventors: Dharam P. Gosain, Jonathan Westwater, Setsuo Usui
  • Patent number: 5567633
    Abstract: A polycrystalline silicon film formed of an active layer of a thin film transistor is entirely hydrogenated by a low-temperature process, thereby lowering the resistance and relaxing the electric field in the vicinity of the drain to reduce the leakage current. A gate and an insulating film that covers it are formed on a substrate having an insulating surface. A hydrogenated polycrystalline silicon film is formed over the substrate, including the gate, with the insulating film interposed therebetween. A silicon oxide film pattern is formed on the polycrystalline silicon film directly above the gate. Source/drain regions are formed on the polycrystalline silicon film substantially at two external sides of the silicon oxide film pattern. The source/drain regions are formed from a hydrogen-containing amorphous silicon film, a conductive silicon film and a metal film, which are successively stacked on the polycrystalline silicon film.
    Type: Grant
    Filed: March 29, 1995
    Date of Patent: October 22, 1996
    Assignee: Sony Corporation
    Inventors: Dharam P. Gosain, Jonathan Westwater, Setsuo Usui
  • Patent number: 5446304
    Abstract: An active layer of an insulated-gate type field effect transistor is formed by a thin film of an intrinsic polycrystalline semiconductor and a source electrode and a drain electrode are formed on the active layer. A source region and a drain region are not formed in the active layer. A main gate electrode is formed on a gate insulating film of a portion between the source electrode and the drain electrode. Subgate electrodes are formed on the gate insulating film in a portion between the source electrode and the main gate electrode and a portion between the drain electrode and the main gate electrode, respectively.
    Type: Grant
    Filed: September 29, 1994
    Date of Patent: August 29, 1995
    Assignee: Sony Corporation
    Inventors: Toshiyuki Sameshima, Naoki Sano, Dharam P. Gosain, Setsuo Usui
  • Patent number: 5437734
    Abstract: Disclosed herein is a solar cell which is composed basically of a first semiconductor layer of first conductivity type, a second semiconductor layer of second conductivity type, and a third semiconductor layer formed between them. The third semiconductor layer has a band gap narrower than that of the first and second semiconductor layers. The third semiconductor layer also has a pn junction therein. The semiconductor layers are each separated by a buffer layer in which the composition changes gradually across the thickness so that the lattice mismatch between the semiconductor layers is relieved.
    Type: Grant
    Filed: February 8, 1994
    Date of Patent: August 1, 1995
    Assignee: Sony Corporation
    Inventors: Takeshi Matsushita, Dharam P. Gosain, Jonathan Westwater, Setsuo Usui, Kunio Hane