Patents by Inventor Dharaneedharan S.

Dharaneedharan S. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Context protection for a column interleaved memory
    Patent number: 8971084
    Abstract: A semiconductor memory cell includes a set of circuit structures, each having column input/output circuits. The semiconductor memory cell further includes a set of replicas corresponding to the column input/output circuits. The set of replicas are non-functional and fills an empty space next to the column input/output circuits and hence, provides context protection for the column input/output circuits.
    Type: Grant
    Filed: July 23, 2013
    Date of Patent: March 3, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Lakshmikantha Holla, Thomas Aton, Steve Prins, Dharaneedharan S
  • CONTEXT PROTECTION FOR A COLUMN INTERLEAVED MEMORY
    Publication number: 20150029773
    Abstract: A semiconductor memory cell includes a set of circuit structures, each having column input/output circuits. The semiconductor memory cell further includes a set of replicas corresponding to the column input/output circuits. The set of replicas are non-functional and fills an empty space next to the column input/output circuits and hence, provides context protection for the column input/output circuits.
    Type: Application
    Filed: July 23, 2013
    Publication date: January 29, 2015
    Applicant: Texas Instruments Incorporated
    Inventors: Lakshmikantha Holla, Thomas ATON, Steve PRINS, Dharaneedharan S.