Patents by Inventor Dharani Kotte
Dharani Kotte has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240362111Abstract: In one embodiment, a solid state drive (SSD) comprises a plurality of non-volatile memory dies communicatively arranged in one or more communication channels, each of the plurality of non-volatile memory dies comprising a plurality of physical blocks, one or more channel controllers communicatively coupled to the one or more communication channels, respectively, and a memory controller communicatively coupled to the plurality of non-volatile memory dies via the one or more channel controllers, wherein the memory controller is configured to assign (i) the plurality of physical blocks of a first die of the plurality of non-volatile memory dies to only a first region and (ii) the plurality of physical blocks of a second die of the plurality of non-volatile memory dies to only a second region, perform only read operations on the first region in a first operation mode, and perform write operations or maintenance operations on the second region in a second operation mode concurrently with read operations on the firType: ApplicationFiled: July 8, 2024Publication date: October 31, 2024Applicant: Kioxia CorporationInventors: Steven Wells, Mark Carlson, Amit Jain, Narasimhulu Dharani Kotte, Senthil Thangaraj, Barada Mishra, Girish Desai
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Patent number: 12032438Abstract: In one embodiment, a solid state drive (SSD) comprises a plurality of non-volatile memory dies communicatively arranged in one or more communication channels, each of the plurality of non-volatile memory dies comprising a plurality of physical blocks, one or more channel controllers communicatively coupled to the one or more communication channels, respectively, and a memory controller communicatively coupled to the plurality of non-volatile memory dies via the one or more channel controllers, wherein the memory controller is configured to assign (i) the plurality of physical blocks of a first die of the plurality of non-volatile memory dies to only a first region and (ii) the plurality of physical blocks of a second die of the plurality of non-volatile memory dies to only a second region, perform only read operations on the first region in a first operation mode, and perform write operations or maintenance operations on the second region in a second operation mode concurrently with read operations on the firType: GrantFiled: March 21, 2022Date of Patent: July 9, 2024Assignee: KIOXIA CORPORATIONInventors: Steven Wells, Mark Carlson, Amit Jain, Narasimhulu Dharani Kotte, Senthil Thangaraj, Barada Mishra, Girish Desai
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Publication number: 20220214834Abstract: In one embodiment, a solid state drive (SSD) comprises a plurality of non-volatile memory dies communicatively arranged in one or more communication channels, each of the plurality of non-volatile memory dies comprising a plurality of physical blocks, one or more channel controllers communicatively coupled to the one or more communication channels, respectively, and a memory controller communicatively coupled to the plurality of non-volatile memory dies via the one or more channel controllers, wherein the memory controller is configured to assign (i) the plurality of physical blocks of a first die of the plurality of non-volatile memory dies to only a first region and (ii) the plurality of physical blocks of a second die of the plurality of non-volatile memory dies to only a second region, perform only read operations on the first region in a first operation mode, and perform write operations or maintenance operations on the second region in a second operation mode concurrently with read operations on the firType: ApplicationFiled: March 21, 2022Publication date: July 7, 2022Inventors: Steven Wells, Mark Carlson, Amit Jain, Narasimhulu Dharani Kotte, Senthil Thangaraj, Barada Mishra, Girish Desai
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Patent number: 11294594Abstract: In one embodiment, a solid state drive (SSD) comprises a plurality of non-volatile memory dies communicatively arranged in one or more communication channels, each of the plurality of non-volatile memory dies comprising a plurality of physical blocks, one or more channel controllers communicatively coupled to the one or more communication channels, respectively, and a memory controller communicatively coupled to the plurality of non-volatile memory dies via the one or more channel controllers, wherein the memory controller is configured to assign (i) the plurality of physical blocks of a first die of the plurality of non-volatile memory dies to only a first region and (ii) the plurality of physical blocks of a second die of the plurality of non-volatile memory dies to only a second region, perform only read operations on the first region in a first operation mode, and perform write operations or maintenance operations on the second region in a second operation mode concurrently with read operations on the firType: GrantFiled: November 1, 2017Date of Patent: April 5, 2022Assignee: Kioxia CorporationInventors: Steven Wells, Mark Carlson, Amit Jain, Narasimhulu Dharani Kotte, Senthil Thangaraj, Barada Mishra, Girish Desai
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Patent number: 10656842Abstract: Systems, methods and/or devices are used to enable using history of I/O sizes and I/O sequences to trigger coalesced writes in a non-volatile storage device. In one aspect, the method includes (1) receiving a plurality of input/output (I/O) requests to be performed in a plurality of regions in a logical address space of a host, and (2) performing one or more operations for each region of the plurality of regions in the logical address space of the host, including (a) determining whether the region has a history of I/O requests to access data of size less than a predefined small-size threshold during a predetermined time period, (b) determining whether the region has a history of sequential write requests during the predetermined time period, and (c) if both determinations are true, coalescing subsequent write requests to the region.Type: GrantFiled: July 3, 2014Date of Patent: May 19, 2020Assignee: SANDISK TECHNOLOGIES LLCInventors: Akshay Mathur, Dharani Kotte, Chayan Biswas, Baskaran Kannan, Sumant K. Patro
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Patent number: 10656840Abstract: Systems, methods and/or devices are used to enable real-time I/O pattern recognition to enhance performance and endurance of a storage device. In one aspect, the method includes (1) at a storage device, receiving from a host a plurality of input/output (I/O) requests, the I/O requests specifying operations to be performed in a plurality of regions in a logical address space of the host, and (2) performing one or more operations for each region of the plurality of regions in the logical address space of the host, including (a) maintaining a history of I/O request patterns in the region for a predetermined time period, and (b) using the history of I/O request patterns in the region to adjust subsequent I/O processing in the region.Type: GrantFiled: July 3, 2014Date of Patent: May 19, 2020Assignee: SanDisk Technologies LLCInventors: Dharani Kotte, Akshay Mathur, Chayan Biswas, Baskaran Kannan, Sumant K. Patro
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Patent number: 10372613Abstract: Systems, methods and/or devices are used to enable using sub-region I/O history to cache repeatedly accessed sub-regions in a non-volatile storage device. In one aspect, the method includes (1) receiving a plurality of input/output (I/O) requests including read requests and write requests to be performed in a plurality of regions in a logical address space of a host, and (2) performing one or more operations for each region of the plurality of regions in the logical address space of the host, including, for each sub-region of a plurality of sub-regions of the region: (a) determining whether the sub-region is accessed more than a predetermined threshold number of times during a predetermined time period, and (b) if so, caching, from a storage medium of the storage device to a cache of the storage device, data from the sub-region.Type: GrantFiled: July 3, 2014Date of Patent: August 6, 2019Assignee: Sandisk Technologies LLCInventors: Akshay Mathur, Dharani Kotte, Chayan Biswas, Baskaran Kannan, Sumant K. Patro
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Publication number: 20190042150Abstract: In one embodiment, a solid state drive (SSD) comprises a plurality of non-volatile memory dies communicatively arranged in one or more communication channels, each of the plurality of non-volatile memory dies comprising a plurality of physical blocks, one or more channel controllers communicatively coupled to the one or more communication channels, respectively, and a memory controller communicatively coupled to the plurality of non-volatile memory dies via the one or more channel controllers, wherein the memory controller is configured to assign (i) the plurality of physical blocks of a first die of the plurality of non-volatile memory dies to only a first region and (ii) the plurality of physical blocks of a second die of the plurality of non-volatile memory dies to only a second region, perform only read operations on the first region in a first operation mode, and perform write operations or maintenance operations on the second region in a second operation mode concurrently with read operations on the firType: ApplicationFiled: November 1, 2017Publication date: February 7, 2019Inventors: Steven Wells, Mark Carlson, Amit Jain, Narasimhulu Dharani Kotte, Senthil Thangaraj, Barada Mishra, Girish Desai
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Patent number: 10162748Abstract: Systems, methods and/or devices are used to enable prioritizing garbage collection and block allocation based on I/O history for logical address regions. In one aspect, the method includes (1) receiving, at a storage device, a plurality of input/output (I/O) requests from a host, the plurality of I/O requests including read requests and write requests to be performed in a plurality of regions in a logical address space of the host, (2) in accordance with the plurality of I/O requests over a predetermined time period, identifying an idle region of the plurality of regions in the logical address space of the host, and (3) in accordance with the identification of the idle region, enabling garbage collection of data storage blocks, in the storage device, that store data in the idle region.Type: GrantFiled: July 3, 2014Date of Patent: December 25, 2018Assignee: SANDISK TECHNOLOGIES LLCInventors: Dharani Kotte, Akshay Mathur, Chayan Biswas, Sumant K. Patro, Baskaran Kannan
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Patent number: 10146448Abstract: Systems, methods and/or devices are used to enable using history of I/O sequences to trigger cached read ahead in a non-volatile storage device. In one aspect, the method includes (1) receiving, at a storage device, a plurality of input/output (I/O) requests from a host, the plurality of I/O requests including read requests and write requests to be performed in a plurality of regions in a logical address space of the host, and (2) performing one or more operations for each region of the plurality of regions in the logical address space of the host, including (a) determining whether the region has a history of sequential read requests during a predetermined time period, and (b) in accordance with a determination that the region has a history of sequential read requests during the predetermined time period, enabling read ahead logic for the region.Type: GrantFiled: July 3, 2014Date of Patent: December 4, 2018Assignee: SANDISK TECHNOLOGIES LLCInventors: Dharani Kotte, Akshay Mathur, Baskaran Kannan, Sumant K. Patro
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Patent number: 10114557Abstract: Systems, methods and/or devices are used to enable identification of hot regions to enhance performance and endurance of a non-volatile storage device. In one aspect, the method includes (1) receiving a plurality of input/output (I/O) requests to be performed in a plurality of regions in a logical address space of a host, and (2) performing one or more operations for each region of the plurality of regions in the logical address space of the host, including (a) determining whether the region is accessed by the plurality of I/O requests more than a predetermined threshold number of times during a predetermined time period, (b) if so, marking the region with a hot region indicator, and (c) while the region is marked with the hot region indicator, identifying open blocks associated with the region, and marking each of the identified open blocks with a hot block indicator.Type: GrantFiled: July 3, 2014Date of Patent: October 30, 2018Assignee: SANDISK TECHNOLOGIES LLCInventors: Dharani Kotte, Akshay Mathur, Chayan Biswas, Sumant K. Patro
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Patent number: 10095626Abstract: A solid state drive (SSD) with pseudo-single-level cell (pSLC) caching and a method of caching data in an SSD is disclosed. In one embodiment, the SSD includes a plurality of multibit NAND media devices arranged in one or more channels communicatively coupled to a memory controller. A first portion of the plurality of multibit NAND media devices is configured to operate as a pSLC cache and a second portion of the plurality of multibit NAND media devices is configured to operate as a multibit NAND media storage area. In one embodiment, the pSLC cache comprises a first area for a pSLC write cache and a second area for a pSLC read cache.Type: GrantFiled: March 10, 2017Date of Patent: October 9, 2018Assignee: Toshiba Memory CorporationInventors: Narasimhulu Dharani Kotte, Senthil Thamgaraj, Robert Reed, Hitoshi Kondo
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Publication number: 20180260342Abstract: A mass storage device and a method for wirelessly transmitting a first information by a mass storage device is disclosed. In one embodiment, the mass storage device includes one or more memory devices and a mass storage device controller communicatively coupled to the one or more memory devices. The mass storage device controller includes one or more controller processors and a wireless sideband interface. The wireless sideband interface is configured to wirelessly transmit the first information retrieved by an interface processor of the wireless sideband interface from one of the controller processors or one of the memory devices. In one embodiment, the interface processor is an internet-of-things (IoT) processor.Type: ApplicationFiled: March 10, 2017Publication date: September 13, 2018Inventors: Senthil Murugan Thangaraj, Narasimhulu Dharani Kotte, Chayan Biswas, Robert Reed, Hitoshi Kondo
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Publication number: 20180260331Abstract: A solid state drive (SSD) with pseudo-single-level cell (pSLC) caching and a method of caching data in an SSD is disclosed. In one embodiment, the SSD includes a plurality of multibit NAND media devices arranged in one or more channels communicatively coupled to a memory controller. A first portion of the plurality of multibit NAND media devices is configured to operate as a pSLC cache and a second portion of the plurality of multibit NAND media devices is configured to operate as a multibit NAND media storage area. In one embodiment, the pSLC cache comprises a first area for a pSLC write cache and a second area for a pSLC read cache.Type: ApplicationFiled: March 10, 2017Publication date: September 13, 2018Inventors: Narasimhulu Dharani Kotte, Senthil Murugan Thangaraj, Robert Reed, Hitoshi Kondo
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Patent number: 10049047Abstract: A solid state drive (SSD) with pseudo-single-level cell (pSLC) caching and a method of caching data in an SSD is disclosed. In one embodiment, the SSD includes a plurality of multibit NAND media devices arranged in one or more channels communicatively coupled to a memory controller. The SSD further includes one or more volatile memory devices communicatively coupled to the memory controller, where at least one of the one or more volatile memory devices has a read cache area. A first portion of the plurality of multibit NAND media devices is configured to operate as a pSLC write cache and a second portion of the plurality of multibit NAND media devices is configured to operate as a multibit NAND media storage area.Type: GrantFiled: March 10, 2017Date of Patent: August 14, 2018Assignee: Toshiba Memory CorporationInventors: Narasimhulu Dharani Kotte, Senthil Thamgaraj, Robert Reed, Hitoshi Kondo
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Patent number: 9703491Abstract: Systems, methods and/or devices are used to enable using history of unaligned writes to cache data and avoid read-modify-writes in a non-volatile storage device. In one aspect, the method includes (1) receiving a plurality of input/output (I/O) requests including read requests and write requests to be performed in a plurality of regions in a logical address space of a host, and (2) performing one or more operations for each region of the plurality of regions in the logical address space of the host, including (a) determining whether the region has a history of unaligned write requests during a predetermined time period, and (b) if so: (i) determining one or more sub-regions within the region that are accessed more than a predetermined threshold number of times during the predetermined time period, and (ii) caching data from the determined one or more sub-regions.Type: GrantFiled: July 3, 2014Date of Patent: July 11, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Akshay Mathur, Dharani Kotte, Chayan Biswas, Baskaran Kannan
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Patent number: 9507711Abstract: In a memory system having non-volatile memory and volatile memory, write data are stored in a write-coalescing buffer in the volatile memory until the write data is written to non-volatile memory. First and second level address mapping tables are stored in the volatile memory and corresponding first and second level address mapping tables are stored in the non-volatile memory, and furthermore the second level address mapping table in the volatile memory contains entries corresponding to only a subset of the entries in the second level address mapping table in the non-volatile memory. The first address-mapping table in volatile memory includes entries storing pointers to entries in the second address-mapping table in volatile memory, entries storing pointers to locations in the write-coalescing buffer, and entries storing pointers to locations in the non-volatile memory that store data.Type: GrantFiled: May 22, 2015Date of Patent: November 29, 2016Assignee: SANDISK TECHNOLOGIES LLCInventors: Dharani Kotte, Akshay Mathur, Satish B. Vasudeva, Sumant K. Patro
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Publication number: 20160342509Abstract: In a memory system having non-volatile memory and volatile memory, write data are stored in a write-coalescing buffer in the volatile memory until the write data is written to non-volatile memory. First and second level address mapping tables are stored in the volatile memory and corresponding first and second level address mapping tables are stored in the non-volatile memory, and furthermore the second level address mapping table in the volatile memory contains entries corresponding to only a subset of the entries in the second level address mapping table in the non-volatile memory. The first address-mapping table in volatile memory includes entries storing pointers to entries in the second address-mapping table in volatile memory, entries storing pointers to locations in the write-coalescing buffer, and entries storing pointers to locations in the non-volatile memory that store data.Type: ApplicationFiled: May 22, 2015Publication date: November 24, 2016Inventors: Dharani Kotte, Akshay Mathur, Satish B. Vasudeva, Sumant K. Patro
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Publication number: 20150347296Abstract: Systems, methods and/or devices are used to enable prioritizing garbage collection and block allocation based on I/O history for logical address regions. In one aspect, the method includes (1) receiving, at a storage device, a plurality of input/output (I/O) requests from a host, the plurality of I/O requests including read requests and write requests to be performed in a plurality of regions in a logical address space of the host, (2) in accordance with the plurality of I/O requests over a predetermined time period, identifying an idle region of the plurality of regions in the logical address space of the host, and (3) in accordance with the identification of the idle region, enabling garbage collection of data storage blocks, in the storage device, that store data in the idle region.Type: ApplicationFiled: July 3, 2014Publication date: December 3, 2015Inventors: Dharani Kotte, Akshay Mathur, Chayan Biswas, Sumant K. Patro, Baskaran Kannan
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Publication number: 20150347028Abstract: Systems, methods and/or devices are used to enable real-time I/O pattern recognition to enhance performance and endurance of a storage device. In one aspect, the method includes (1) at a storage device, receiving from a host a plurality of input/output (I/O) requests, the I/O requests specifying operations to be performed in a plurality of regions in a logical address space of the host, and (2) performing one or more operations for each region of the plurality of regions in the logical address space of the host, including (a) maintaining a history of I/O request patterns in the region for a predetermined time period, and (b) using the history of I/O request patterns in the region to adjust subsequent I/O processing in the region.Type: ApplicationFiled: July 3, 2014Publication date: December 3, 2015Inventors: Dharani Kotte, Akshay Mathur, Chayan Biswas, Baskaran Kannan, Sumant K. Patro