Patents by Inventor Dharin Shah
Dharin Shah has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9576621Abstract: A static random-access memory (SRAM) in an integrated circuit with circuitry for timing the enabling of sense amplifiers. The memory includes read/write SRAM cells, along with word-line tracking transistors arranged in one or more rows along a side of the read/write cells, and read-tracking transistors arranged in a column along a side of the read/write cells. A reference word line extends over the word-line tracking transistors, with its far end from the driver connected to pass transistors in the read-tracking transistors. The read-tracking transistors are preset to a known data state that, when accessed responsive to the reference word line, discharges a reference bit line, which in turn drives a sense amplifier enable signal.Type: GrantFiled: May 21, 2013Date of Patent: February 21, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Anand Seshadri, Dharin Shah, Parvinder Rana, Wah Kit Loh
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Publication number: 20140010032Abstract: A static random-access memory (SRAM) in an integrated circuit with circuitry for timing the enabling of sense amplifiers. The memory includes read/write SRAM cells, along with word-line tracking transistors arranged in one or more rows along a side of the read/write cells, and read-tracking transistors arranged in a column along a side of the read/write cells. A reference word line extends over the word-line tracking transistors, with its far end from the driver connected to pass transistors in the read-tracking transistors. The read-tracking transistors are preset to a known data state that, when accessed responsive to the reference word line, discharges a reference bit line, which in turn drives a sense amplifier enable signal.Type: ApplicationFiled: May 21, 2013Publication date: January 9, 2014Applicant: Texas Instruments IncorporatedInventors: Anand Seshadri, Dharin Shah, Parvinder Rana, Wah Kit Loh
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Patent number: 7895551Abstract: Generating cells with increased signal routing resources. In an embodiment, power and ground buses in a metal layer of a source cell are identified and removed. Any vias terminating on the removed buses may also be removed. Additional via and connections are added to other desired layers to provide connectivity to the nodes disconnected due to the earlier removal. According to an aspect of the present invention, such connections are added during a chip design phase (i.e., when the cell instances are incorporated into an integrated circuit, sought to be designed).Type: GrantFiled: May 21, 2008Date of Patent: February 22, 2011Assignee: Texas Instruments IncorporatedInventors: Dharin Shah, Clive David Bittlestone, Graham McLeod Barr, Girishankar Gurumurthy, Pavan Vithal Torvi
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Publication number: 20090293023Abstract: Generating cells with increased signal routing resources. In an embodiment, power and ground buses in a metal layer of a source cell are identified and removed. Any vias terminating on the removed buses may also be removed. Additional via and connections are added to other desired layers to provide connectivity to the nodes disconnected due to the earlier removal. According to an aspect of the present invention, such connections are added during a chip design phase (i.e., when the cell instances are incorporated into an integrated circuit, sought to be designed).Type: ApplicationFiled: May 21, 2008Publication date: November 26, 2009Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Dharin Shah, Clive David Bittlestone, Graham McLeod Barr, Girishankar Gurumurthy, Pavan Vithal Torvi
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Patent number: 7564077Abstract: An integrated circuit. The integrated circuit comprises an area having a layout aligned in rows. Each row is definable by a pair of row boundaries. The integrated circuit also comprises a plurality of cells, comprising a first set of cells. Each cell in the first set of cells spans at least two rows and comprises a PMOS transistor having a source/drain region that spans across one of the row boundaries and an NMOS transistor having a source/drain region that spans across one of the row boundaries.Type: GrantFiled: May 7, 2007Date of Patent: July 21, 2009Assignee: Texas Instruments IncorporatedInventors: Uming Ko, Dharin Shah, Senthil Sundaramoorthy, Girishankar Gurumurthy, Sumanth Gururajarao, Rolf Lagerquist, Clive Bittlestone
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Publication number: 20070290270Abstract: An integrated circuit. The integrated circuit comprises an area having a layout aligned in rows. Each row is definable by a pair of row boundaries. The integrated circuit also comprises a plurality of cells, comprising a first set of cells. Each cell in the first set of cells spans at least two rows and comprises a PMOS transistor having a source/drain region that spans across one of the row boundaries and an NMOS transistor having a source/drain region that spans across one of the row boundaries.Type: ApplicationFiled: May 7, 2007Publication date: December 20, 2007Inventors: Uming Ko, Dharin Shah, Senthil Sundaramoorthy, Girishankar Gurumurthy, Sumanth Gururajarao, Rolf Lagerquist, Clive Bittlestone
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Publication number: 20070022344Abstract: A digital storage element (e.g., a flip-flop or a latch) comprise a master transparent latch that receives functional data from a data input port and scan data from a scan input port and a slave transparent latch coupled to said master transparent latch. The slave transparent latch comprises dedicated functional data and scan data output ports. The digital storage element operates in a functional mode or in a scan mode. While in the scan mode, a first clock signal is used by the slave transparent latch and a second clock signal is used by the master transparent latch. The first and second clock signals are non-overlapping and, as such, avoid the digital storage element from creating hold violations.Type: ApplicationFiled: June 30, 2005Publication date: January 25, 2007Applicant: Texas Instruments IncorporatedInventors: Charles Branch, Steven Bartling, Dharin Shah
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Publication number: 20070022336Abstract: A digital storage element (e.g., a flip-flop or a latch) comprise a master transparent latch that receives functional data from a data input port and scan data from a scan input port and a slave transparent latch coupled to the master transparent latch. The slave transparent latch comprises dedicated functional data and scan data output ports. A clock gating element is also included that gates off a clock to the slave latch, and not the master transparent latch, based on an enable signal that is asserted to disable use of the digital storage element.Type: ApplicationFiled: June 30, 2005Publication date: January 25, 2007Applicant: Texas Instruments IncorporatedInventors: Charles Branch, Steven Bartling, Dharin Shah
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Publication number: 20070001730Abstract: A digital storage element comprises a master transparent latch that receives functional data signals from data input ports and scan data signals from a scan input port, the data input ports coupled to a four-input, one-output multiplexer adapted to receive the functional data signals and to selectively output one of the functional data signals. The digital storage element also comprises a slave transparent latch coupled to the master transparent latch, the slave transparent latch comprising dedicated functional data and scan data output ports. While operating in a scan mode, a first clock signal is used by the slave transparent latch and a second clock signal is used by the master transparent latch, wherein the first and second clock signals are non-overlapping.Type: ApplicationFiled: June 30, 2005Publication date: January 4, 2007Applicant: Texas Instruments IncorporatedInventors: Charles Branch, Steven Bartling, Dharin Shah
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Publication number: 20070001732Abstract: A digital storage element comprises a master transparent latch that receives functional data from a data input port and scan data from a scan input port and a slave transparent latch coupled to the master transparent latch. The slave transparent latch comprises dedicated functional data and scan data output ports. The master and slave transparent latches have opposite transparent polarities when in a functional mode and have the same polarities (e.g., positive level sense) when in a scan mode. The transparent polarity of a transparent latch defines the state of a clock to that latch for which the transparent latch is transparent.Type: ApplicationFiled: June 30, 2005Publication date: January 4, 2007Applicant: Texas Instruments IncorporatedInventors: Charles Branch, Steven Bartling, Dharin Shah, James Hochschild
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Publication number: 20070001731Abstract: A digital storage element comprises a master transparent latch that receives functional data signals from data input ports and scan data signals from a scan input port, the data input ports coupled to a four-input, one-output multiplexer that receives the functional data signals and selectively outputs one of the functional data signals. The element comprises a slave transparent latch coupled to the master transparent latch and comprising dedicated functional and scan data output ports. While operating in a scan mode, a first clock signal is used by the slave transparent latch and a second clock signal is used by the master transparent latch, wherein the first and second clock signals are non-overlapping. A first transistor is coupled to the master transparent latch and a second transistor is coupled to the slave transparent latch. When activated, the first or second transistor resets the element.Type: ApplicationFiled: June 30, 2005Publication date: January 4, 2007Applicant: Texas Instruments IncorporatedInventors: Charles Branch, Steven Bartling, Dharin Shah
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Publication number: 20070001733Abstract: A digital storage element comprises a master transparent latch that receives functional data signals from data input ports and scan data signals from a scan input port. The data input ports are coupled to a two-input, one-output multiplexer adapted to receive the functional data signals and to selectively output one of the functional data signals. The digital storage element also comprises a slave transparent latch coupled to the master transparent latch, the slave transparent latch comprising dedicated functional data and scan data output ports. While operating in a scan mode, a first clock signal is used by the slave transparent latch and a second clock signal is used by the master transparent latch, wherein the first and second clock signals are non-overlapping.Type: ApplicationFiled: June 30, 2005Publication date: January 4, 2007Applicant: Texas Instruments IncorporatedInventors: Charles Branch, Steven Bartling, Dharin Shah