Patents by Inventor DHARMARAY NEDALGI

DHARMARAY NEDALGI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • TRANSISTOR OVER-VOLTAGE PROTECTION
    Publication number: 20240088887
    Abstract: An apparatus comprises a first supply node to provide a first voltage and a second supply node to provide a second voltage lower than the first voltage. First and second transistors, of a first conductivity type, are coupled in series at a first common node, wherein the first transistor is coupled to the first supply node, and the second transistor is coupled to an output node. Third and fourth transistors, of a second conductivity type, coupled in series at a second common node, wherein the fourth transistor is coupled to a third node that is to provide a third voltage, and the third transistor is coupled to the output node. First impedance circuitry is coupled to a gate terminal of the second transistor, the second supply node, and to a gate terminal of the first transistor.
    Type: Application
    Filed: November 23, 2022
    Publication date: March 14, 2024
    Applicant: Intel Corporation
    Inventors: Dharmaray Nedalgi, Lavanya Manohar Nirikhi
  • Back power protection circuit
    Patent number: 10938200
    Abstract: Described is an apparatus which comprises: one or more signal lines; a transceiver coupled to the one or more signal lines; and a bias generation circuit to provide one or more bias voltages for the transceiver to tri-state the transceiver according to signal attributes of the one or more signal lines.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: March 2, 2021
    Assignee: Intel Corporation
    Inventors: Amit Kumar Srivastava, Karthik Ns, Raghavendra Devappa Sharma, Dharmaray Nedalgi, Prasad Bhilawadi
  • Apparatus and method for over-voltage protection
    Patent number: 10693450
    Abstract: An apparatus is provided which comprises: a dual stack voltage driver, wherein the dual stack voltage driver comprises a first stack of transistors, and a second stack of transistors; and one or more feedback transistors each coupled to a transistor of the second stack of transistors.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: June 23, 2020
    Assignee: Intel IP Corporation
    Inventors: Dharmaray Nedalgi, Karthik Ns, Vani Deshpande, Leonhard Heiss
  • Aging tolerant apparatus
    Patent number: 10128248
    Abstract: An apparatus is provided which comprises: a stack of transistors of a same conductivity type, the stack including a first transistor and a second transistor coupled in series and having a common node; and a feedback transistor of the same conductivity type coupled to the common node and a gate terminal of the first transistor of the stack.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: November 13, 2018
    Assignee: Intel Corporation
    Inventors: Karthik Ns, Dharmaray Nedalgi, Vani Deshpande, Leonhard Heiss, Amit Kumar Srivastava
  • BACK POWER PROTECTION CIRCUIT
    Publication number: 20170170646
    Abstract: Described is an apparatus which comprises: one or more signal lines; a transceiver coupled to the one or more signal lines; and a bias generation circuit to provide one or more bias voltages for the transceiver to tri-state the transceiver according to signal attributes of the one or more signal lines.
    Type: Application
    Filed: February 27, 2017
    Publication date: June 15, 2017
    Inventors: Amit Kumar SRIVASTAVA, Karthik NS, Raghavendra Devappa SHARMA, Dharmaray NEDALGI, Prasad BHILAWADI
  • Back power protection circuit
    Patent number: 9601916
    Abstract: Described is an apparatus which comprises: one or more signal lines; a transceiver coupled to the one or more signal lines; and a bias generation circuit to provide one or more bias voltages for the transceiver to tri-state the transceiver according to signal attributes of the one or more signal lines.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: March 21, 2017
    Assignee: Intel Corporation
    Inventors: Amit Kumar Srivastava, Karthik Ns, Raghavendra Devappa Sharma, Dharmaray Nedalgi, Prasad Bhilawadi
  • BACK POWER PROTECTION CIRCUIT
    Publication number: 20160079747
    Abstract: Described is an apparatus which comprises: one or more signal lines; a transceiver coupled to the one or more signal lines; and a bias generation circuit to provide one or more bias voltages for the transceiver to tri-state the transceiver according to signal attributes of the one or more signal lines.
    Type: Application
    Filed: September 11, 2014
    Publication date: March 17, 2016
    Inventors: Amit Kumar Srivastava, KARTHIK NS, RAGHAVENDRA DEVAPPA SHARMA, DHARMARAY NEDALGI, PRASAD BHILAWADI