Patents by Inventor Dharmendar Reddy Palle

Dharmendar Reddy Palle has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Bi-layer pseudo-spin field-effect transistor
    Patent number: 8263967
    Abstract: A bi-layer pseudo-spin field-effect transistor (BiSFET) is disclosed. The BiSFET includes a first and second conduction layers separated by a tunnel dielectric. The BiSFET transistor also includes a first gate separated from the first conduction layer by an insulating dielectric layer, and a second gate separated from the second conduction layer by an insulating layer. These conduction layers may be composed of graphene. The voltages applied to the first and/or second gates can control the peak current and associated voltage value for current flow between top and bottom conduction channels, and interlayer current voltage characteristic exhibiting negative differential resistance. BiSFETs may be used to make a variety of logic gates. A clocked power supply scheme may be used to facilitate BiSFET-based logic.
    Type: Grant
    Filed: May 1, 2012
    Date of Patent: September 11, 2012
    Assignee: Board of Regents, The University of Texas Systems
    Inventors: Sanjay K. Banerjee, Leonard Franklin Register, II, Allan MacDonald, Dharmendar Reddy Palle, Emanuel Tutuc
  • BI-LAYER PSEUDO-SPIN FIELD-EFFECT TRANSISTOR
    Publication number: 20120212257
    Abstract: A bi-layer pseudo-spin field-effect transistor (BiSFET) is disclosed. The BiSFET includes a first and second conduction layers separated by a tunnel dielectric. The BiSFET transistor also includes a first gate separated from the first conduction layer by an insulating dielectric layer, and a second gate separated from the second conduction layer by an insulating layer. These conduction layers may be composed of graphene. The voltages applied to the first and/or second gates can control the peak current and associated voltage value for current flow between top and bottom conduction channels, and interlayer current voltage characteristic exhibiting negative differential resistance. BiSFETs may be used to make a variety of logic gates. A clocked power supply scheme may be used to facilitate BiSFET-based logic.
    Type: Application
    Filed: May 1, 2012
    Publication date: August 23, 2012
    Inventors: Sanjay K. Banerjee, Leonard Franklin Register, II, Allan MacDonald, Dharmendar Reddy Palle, Emanuel Tutuc
  • Bi-layer pseudo-spin field-effect transistor
    Patent number: 8188460
    Abstract: A bi-layer pseudo-spin field-effect transistor (BiSFET) is disclosed. The BiSFET includes a first and second conduction layers separated by a tunnel dielectric. The BiSFET transistor also includes a first gate separated from the first conduction layer by an insulating dielectric layer, and a second gate separated from the second conduction layer by an insulating layer. These conduction layers may be composed of graphene. The voltages applied to the first and/or second gates can control the peak current and associated voltage value for current flow between top and bottom conduction channels, and interlayer current voltage characteristic exhibiting negative differential resistance. BiSFETs may be used to make a variety of logic gates. A clocked power supply scheme may be used to facilitate BiSFET-based logic.
    Type: Grant
    Filed: November 24, 2009
    Date of Patent: May 29, 2012
    Assignee: Board of Regents, The University of Texas System
    Inventors: Sanjay K. Banerjee, Leonard Franklin Register, II, Allan MacDonald, Dharmendar Reddy Palle, Emanuel Tutuc
  • BI-LAYER PSEUDO-SPIN FIELD-EFFECT TRANSISTOR
    Publication number: 20100127243
    Abstract: A bi-layer pseudo-spin field-effect transistor (BiSFET) is disclosed. The BiSFET includes a first and second conduction layers separated by a tunnel dielectric. The BiSFET transistor also includes a first gate separated from the first conduction layer by an insulating dielectric layer, and a second gate separated from the second conduction layer by an insulating layer. These conduction layers may be composed of graphene. The voltages applied to the first and/or second gates can control the peak current and associated voltage value for current flow between top and bottom conduction channels, and interlayer current voltage characteristic exhibiting negative differential resistance. BiSFETs may be used to make a variety of logic gates. A clocked power supply scheme may be used to facilitate BiSFET-based logic.
    Type: Application
    Filed: November 24, 2009
    Publication date: May 27, 2010
    Applicant: The Board of Regents The University of Texas System
    Inventors: Sanjay K. Banerjee, Leonard Franklin Register, II, Allan MacDonald, Dharmendar Reddy Palle, Emmanuel Tutuc