Abstract: A memory cell array includes local input/output logic configured to access memory cells in memory banks. The memory cell array includes inner memory banks disposed in either direction from the local input/output logic. The memory cell array includes outer memory banks disposed beyond the inner memory banks in either direction from the local input/output logic. The memory cell array further includes local bitlines that run in a lower metallization layer of each of the memory banks. The local bitlines of the outer memory banks connect to the local input/output logic via an upper metallization layer across regions of the inner memory banks.

Abstract: Word line decoders for dual rail SRAM devices are disclosed for high performance sub-micron SRAM designs. One embodiment is an SRAM device that includes a memory cell array and a word line traversing the memory cell array for selecting memory cells of the memory cell array. A row decode-driver coupled to the word line toggles the word line between logic levels of a memory cell supply based on select signals that toggle between logic levels of a peripheral supply. The row decoder-driver toggles the word line without utilizing level shifters along the word line access path.

Abstract: A memory includes a number of storage elements connected to a pair of bit-lines, a bit-line pre-charging circuit, a sense amplifier connected to the pair of bit-lines through a column-select switch, a transition detection circuit connected to an output of the sense amplifier, and a local pre-charge control circuit connected to the transition detection circuit and having a local pre-charge control signal output connected to the bit-line pre-charging circuit.

Abstract: Level shifters are disclosed for high performance sub-micron IC designs. One embodiment is a level shifting device that comprises a first input circuit that toggles a first internal signal between a logical zero of a first voltage range and a logical one of a second voltage range based on an input data signal and an output data signal, and a second input circuit that toggles a second internal signal between a logical zero of the second voltage range and a logical one of the first voltage range based on the input data signal and the output data signal. An output circuit of the device toggles the output data signal between a logical zero of the second voltage range and a logical one of the second voltage range based on the first internal signal, the second internal signal, and a compliment of the input data signal.

Abstract: One exemplary embodiment involves receiving a request for a document key for accessing a document on a client device. The request comprises a user identity identifying a requester requesting access to the document. The request also comprises information about the document. The exemplary embodiment further involves determining, at the server, whether access to the document by the requester is permitted. And, the exemplary embodiment further involves, if access to the document is permitted computing, at the server, the document key using the user identity and using the information about the document. The document key is document specific and, prior to the computing of the document key, the document key is not stored for access by the server. The exemplary embodiment further involves responding to the request by providing the document key for use in accessing the document on the client device.

Abstract: Word line assist circuits are disclosed for high performance sub-micron SRAM designs. One embodiment is an SRAM device that includes a memory cell array and a pair of word lines that traverse the memory cell array for selecting memory cells. The SRAM device further includes a pair of word line drivers, each coupled to one of the word lines. The SRAM device further includes a word line assist circuit coupled to the pair of word lines that receives an enable signal. Responsive to receiving the enable signal, the word line assist circuit assists the first word line driver and the second word line driver in transitioning their respective word lines from a logic level zero to a logic level one in response to a voltage differential between the word lines.

Abstract: Systems and methods presented herein provide for integrated read/write tracking in an SRAM device. In one embodiment, an SRAM device includes a clock, a memory cell array, a column of dummy bit cells operable to mirror bit line loading of the memory cell array, and a row of dummy bit cells operable to mirror word line loading of the memory cell array. The SRAM devices also includes a read/write tracking cell operable to track read operations from the memory cell array via the dummy bit cells, to track write operations to the memory cell array via the dummy bit cells, and to reset the clock based on the tracked read operations and the tracked write operations.

Abstract: In one embodiment, a self-timed, dual-rail SRAM includes a self-timing circuit having a logic gate that is powered by voltage VDD and configured to receive a fire-sense-amplifier timing signal and to produce a VDD-domain sense-amplifier-enable signal SOELV. The self-timing circuit includes an inverting level-shifter having complementary N-type and P-type transistors connected in series between voltage VDDA and ground. The N-type transistor's gate is connected to signal SOELV, and both transistors' drain terminals are connected together to produce output signal SOEHVB. The inverting level-shifter also includes two series-connected P-type transistors connected (i) between supply voltage VDDA and the output and (ii) in parallel with the first P-type (pull-up) transistor. An inverter is connected between the output node and the control terminal of one of the series transistors, and the other series-transistor's gate is connected to signal SOELV.

Abstract: In certain embodiments, a method and apparatus for adjusting the timing of a sense-amplifier read operation in an SRAM integrated memory circuit to overcome process-and-temperature variations are disclosed. A charge-injection pull-up transistor is provided to adjust the rate at which a signal line (e.g., a tracking bit line (TBL) and/or a clock signal (e.g., GCLKB)) transitions from one voltage level to another voltage level. A process-and-temperature-dependent bias circuit is provided to control the charge-injection pull-up transistor. The bias circuit causes the charge-injection pull-up transistor to adjust the discharge rate or transition rate of the signal line to compensate for timing delays caused by process or temperature variations.

Abstract: One embodiment is an apparatus that has a memory array, a discharge device, and a discharge assistance controller. The memory array has memory cells arranged in at least one column that is coupled to a read bit line, and the discharge device is configured to provide discharge assistance to the read bit line. The discharge assistance controller is configured to modify duration of the discharge assistance in correlation with capacitance of the read bit line.

Abstract: A write-tracking circuit for a writable memory array has one or more dummy memory cells and is configured to write different values to the one or more dummy memory cells. Durations of pulses applied to word lines of the memory array during write operations are controlled based on durations of writing the different values to the one or more dummy memory cells. In at least some embodiments, the write-tracking circuit is configured to write the different values to the one or more dummy memory cells during a single write operation. In at least some embodiments, the write-tracking circuit is configured to write the different values to at least one of the one or more dummy memory cells during different write operations.

Abstract: A write-tracking circuit for a writable memory array has one or more dummy memory cells and is configured to write different values to the one or more dummy memory cells. Durations of pulses applied to word lines of the memory array during write operations are controlled based on durations of writing the different values to the one or more dummy memory cells. In at least some embodiments, the write-tracking circuit is configured to write the different values to the one or more dummy memory cells during a single write operation. In at least some embodiments, the write-tracking circuit is configured to write the different values to at least one of the one or more dummy memory cells during different write operations.

Abstract: A memory device having an array of memory cells and BTI-independent bias circuitry for controlling the bias voltage level of a source node of the array. The bias circuitry has an n-type transistor and a p-type transistor connected in parallel between ground and the source node. The bias circuitry also has circuitry for controlling the n-type and p-type transistors such that the memory device can be selectively configured in any of an active mode (where the source node is driven towards ground such that the array can be accessed), a low-leakage-current light sleep mode (where the source node is driven towards an intermediate, data-retention voltage level such that the array cannot be accessed but will retain data), and an even-lower-leakage-current shutdown mode (where the source node is driven towards the power supply voltage level such that the array cannot be accessed and cannot retain data).

Abstract: Apparatuses for measuring rheological properties of fluids and methods for using same are provided. In a general embodiment, the present disclosure provides a mixer sensor that is configured to be attached to a rheometer drive head and used to measure rheological properties of a fluid having particulates over a wide range of temperatures and shear rates. Apparatuses capable of obtaining rheological data of a fluid having particulates over a wide range of temperatures and shear rates provides for more precise rheological measurements. The temperatures may be very high temperatures that exceed 100° C., and the shear rates may includes a range of shear rates that are typically found in a processing pipeline system.

Abstract: One exemplary embodiment involves receiving a request for a document key for accessing a document on a client device. The request comprises a user identity identifying a requester requesting access to the document. The request also comprises information about the document. The exemplary embodiment further involves determining, at the server, whether access to the document by the requester is permitted. And, the exemplary embodiment further involves, if access to the document is permitted computing, at the server, the document key using the user identity and using the information about the document. The document key is document specific and, prior to the computing of the document key, the document key is not stored for access by the server. The exemplary embodiment further involves responding to the request by providing the document key for use in accessing the document on the client device.

Abstract: A memory device comprises a memory block, a power gating transistor, and control circuitry. The memory block includes at least one memory cell comprising a storage element electrically connected to a source potential line, a drive strength of the storage element being a function of a voltage level on the source potential line. The power gating transistor, in turn, is connected between the source potential line and a voltage source. The control circuitry is operative to configure the power gating transistor to electrically connect the source potential line to the voltage source while the memory block is in a first mode, and to clamp the source potential line at a voltage different from that of the voltage source when the memory block is in a second mode.

Abstract: A memory device comprises a memory block, a power gating transistor, and control circuitry. The memory block includes at least one memory cell comprising a storage element electrically connected to a source potential line, a drive strength of the storage element being a function of a voltage level on the source potential line. The power gating transistor, in turn, is connected between the source potential line and a voltage source. The control circuitry is operative to configure the power gating transistor to electrically connect the source potential line to the voltage source while the memory block is in a first mode, and to clamp the source potential line at a voltage different from that of the voltage source when the memory block is in a second mode.

Abstract: A process for the preparation of hydrotreating catalyst which comprises of a Group VIB metal and Group VIII metal on an active composite carrier for the removal of sulfur from gas oil feed stocks, wherein the said carrier comprises of a phosphated alumina and an ultra stable Y zeolite and the metal components mostly reside on the alumina, said process comprising the steps of impregnation of chelated metal complex preferentially on to the alumina component of the composite support and subjecting the composite catalyst to a high-speed ball milling. The catalyst obtained by the process of the present invention consists of the active metals in the nanoparticle range (less than 50 ?) while also retaining the zeolite properties of the composite carrier and the catalyst produces less than 50 ppm sulfur from gas oil feed stocks containing greater than 1 wt % sulfur under typical commercial operating conditions.

Abstract: A satellite-based digital broadcast system is used to provide real-time news, entertainment and informational programs to aircraft passengers in flight. Transmissions from the satellite occur on a time division multiplex (TDM) downlink with different broadcast programs being transmitted on different TDM channels. A broadcast receiver is carried on board the aircraft, and includes a demultiplexer for demultiplexing the TDM channels to reproduce the original broadcast programs. The broadcast receiver may be adapted to receive and reproduce both audio and video broadcasts, as well as to provide other types of information delivery services. Encryption of the broadcast programs may be used to restrict their use to a specific aircraft or airline company.

Abstract: The present invention is related to the development of a new and chromosomally distinct vegetatively propagated frost resisted plant of Cymbopogon flexuosus by genetic selection in open pollinated seed progeny of high yielding variety ‘Cauvery’. The selected plant with stay-green habit withstands prolonged frosting in chilling winter and capable of giving an additional harvest during winter, which is not observed so far in normal varieties.