Patents by Inventor Dharmendra Modha
Dharmendra Modha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11270193Abstract: A scalable stream synaptic supercomputer for extreme throughput neural networks is provided. The firing state of a plurality of neurons of a first neurosynaptic core is determined substantially in parallel. The firing state of the plurality of neurons is delivered to at least one additional neurosynaptic core substantially in parallel.Type: GrantFiled: September 30, 2016Date of Patent: March 8, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Dharmendra Modha
-
Patent number: 10635969Abstract: Core utilization optimization by dividing computational blocks across neurosynaptic cores is provided. In some embodiments, a neural network description describing a neural network is read. The neural network comprises a plurality of functional units on a plurality of cores. A functional unit is selected from the plurality of functional units. The functional unit is divided into a plurality of subunits. The plurality of subunits are connected to the neural network in place of the functional unit. The plurality of functional units and the plurality of subunits are reallocated between the plurality of cores. One or more unused cores are removed from the plurality of cores. An optimized neural network description is written based on the reallocation.Type: GrantFiled: October 14, 2016Date of Patent: April 28, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Arnon Amir, Pallab Datta, Nimrod Megiddo, Dharmendra Modha
-
Patent number: 10338629Abstract: Reduction in the number of neurons and axons in a neurosynaptic network while maintaining its functionality is provided. A neural network description describing a neural network is read. One or more functional unit of the neural network is identified. The one or more functional unit of the neural network is optimized. An optimized neural network description is written based on the optimized functional unit.Type: GrantFiled: September 22, 2016Date of Patent: July 2, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Arnon Amir, Pallab Datta, Dharmendra Modha
-
Publication number: 20180107918Abstract: Core utilization optimization by dividing computational blocks across neurosynaptic cores is provided. In some embodiments, a neural network description describing a neural network is read. The neural network comprises a plurality of functional units on a plurality of cores. A functional unit is selected from the plurality of functional units. The functional unit is divided into a plurality of subunits. The plurality of subunits are connected to the neural network in place of the functional unit. The plurality of functional units and the plurality of subunits are reallocated between the plurality of cores. One or more unused cores are removed from the plurality of cores. An optimized neural network description is written based on the reallocation.Type: ApplicationFiled: October 14, 2016Publication date: April 19, 2018Inventors: Arnon Amir, Pallab Datta, Nimrod Megiddo, Dharmendra Modha
-
Publication number: 20180096242Abstract: A scalable stream synaptic supercomputer for extreme throughput neural networks is provided. The firing state of a plurality of neurons of a first neurosynaptic core is determined substantially in parallel. The firing state of the plurality of neurons is delivered to at least one additional neurosynaptic core substantially in parallel.Type: ApplicationFiled: September 30, 2016Publication date: April 5, 2018Inventor: Dharmendra Modha
-
Publication number: 20180082182Abstract: Reduction in the number of neurons and axons in a neurosynaptic network while maintaining its functionality is provided. A neural network description describing a neural network is read. One or more functional unit of the neural network is identified. The one or more functional unit of the neural network is optimized. An optimized neural network description is written based on the optimized functional unit.Type: ApplicationFiled: September 22, 2016Publication date: March 22, 2018Inventors: Arnon Amir, Pallab Datta, Dharmendra Modha
-
Publication number: 20070250660Abstract: A technique for determining when to destage write data from a fast, NVS of a computer system from an upper level to a lower level of storage in the computer system comprises adaptively varying a destage rate of the NVS according to a current storage occupancy of the NVS; maintaining a high threshold level for the NVS; maintaining a low threshold level that is set to be a predetermined fixed amount below the high threshold; setting the destage rate of the NVS to zero when the NVS occupancy is below the low threshold; setting the destage rate of the NVS to be maximum when the NVS occupancy is above the high threshold; linearly increasing the destage rate of the NVS from zero to maximum as the NVS occupancy goes from the low to the high threshold; and adaptively varying the high threshold in response to a dynamic computer storage workload.Type: ApplicationFiled: April 20, 2006Publication date: October 25, 2007Applicant: International Business Machines CorporationInventors: Binny Gill, Dharmendra Modha
-
Publication number: 20070220200Abstract: A storage system has a storage controller for an array of storage disks, the array being ordered in an sequence of write groups. A write cache is shared by the disks. The storage controller temporarily stores write groups in the write cache responsive to write groups being written to their respective arrays. The write groups are assigned to a global queue ordered by ages. The controller selects a quantity of write groups for attempted destaging to the arrays responsive to a predetermined high threshold for the global queue and to sizes and the ages of the write groups in the global queue, and allocates the selected quantity among the arrays responsive to quantities of certain ones of the write groups in the global queue. Write groups are destaged to respective arrays responsive to the selected allocation quantity for the array and the sequences of the write groups in the arrays.Type: ApplicationFiled: March 20, 2006Publication date: September 20, 2007Inventors: Binny Gill, Dharmendra Modha
-
Publication number: 20070220201Abstract: A storage system has a storage controller for an array of storage disks, the array being ordered in an sequence of write groups. A write cache is shared by the disks. The storage controller temporarily stores write groups in the write cache, responsive to write groups being written, and lists the write groups in order of their sequence in the array and in circular fashion, so that a lowest is listed next to a highest one of the write groups. The storage controller selects the listed write groups in rotating sequence. Such a write group is destaged from the write cache to the disk responsive to i) the selecting of the write group and ii) a state of a recency indicator for the write group, wherein the recency indicator shows recency of writing to the write group.Type: ApplicationFiled: March 20, 2006Publication date: September 20, 2007Inventors: Binny Gill, Dharmendra Modha
-
Publication number: 20070118695Abstract: In a data storage controller, accessed tracks are temporarily stored in a cache, with write data being stored in a first cache (such as a volatile cache) and a second cache and read data being stored in a second cache (such as a non-volatile cache). Corresponding least recently used (LRU) lists are maintained to hold entries identifying the tracks stored in the caches. When the list holding entries for the first cache (the A list) is full, the list is scanned to identify unmodified (read) data which can be discarded from the cache to make room for new data. Prior to or during the scan, modified (write) data entries are moved to the most recently used (MRU) end of the list, allowing the scans to proceed in an efficient manner and reducing the number of times the scan has to skip over modified entries Optionally, a status bit may be associated with each modified data entry.Type: ApplicationFiled: November 18, 2005Publication date: May 24, 2007Applicant: International Business Machines CorporationInventors: Steven Lowe, Dharmendra Modha, Binny Gill, Joseph Hyde
-
Publication number: 20060129782Abstract: An apparatus, system, and method are disclosed for dynamically allocating main memory among applications. The apparatus includes a cache memory module configured to maintain a first list and a second list, each list having a plurality of pages, and a resize module configured to resize the cache by adaptively selecting the first or second list and subtracting pages from or adding pages to the selected list. The system includes the apparatus and a cache replacement module configured to adaptively distribute a workload between the first list and the second list. The method includes maintaining a first list and a second list, each list having a plurality of pages, maintaining a cache memory module having a selected size, and resizing the selected size by adaptively selecting the first or second list and adding pages to the selected list to increase the selected size and subtracting pages from the selected list to decrease the selected size.Type: ApplicationFiled: December 15, 2004Publication date: June 15, 2006Inventors: Sorav Bansal, Paul McKenney, Dharmendra Modha
-
Publication number: 20060080510Abstract: A method is disclosed to manage a data cache. The method provides a data cache comprising a plurality of tracks, where each track comprises one or more segments. The method further maintains a first LRU list comprising one or more first tracks having a low reuse potential, maintains a second LRU list comprising one or more second tracks having a high reuse potential, and sets a target size for the first LRU list. The method then accesses a track, and determines if that accessed track comprises a first track. If the method determines that the accessed track comprises a first track, then the method increases the target size for said first LRU list. Alternatively, if the method determines that the accessed track comprises a second track, then the method decreases the target size for said first LRU list. The method demotes tracks from the first LRU list if its size exceeds the target size; otherwise, the method evicts tracks from the second LRU list.Type: ApplicationFiled: October 12, 2004Publication date: April 13, 2006Inventors: Michael Benhase, Binny Gill, Thomas Jarvis, Dharmendra Modha
-
Publication number: 20060069876Abstract: A method and system of managing data retrieval in a computer comprising a cache memory and auxiliary memory comprises organizing pages in the cache memory into a first and second clock list, wherein the first clock list comprises pages with short-term utility and the second clock list comprises pages with long-term utility; requesting retrieval of a particular page in the computer; identifying requested pages located in the cache memory as a cache hit; transferring requested pages located in the auxiliary memory to the first clock list; relocating the transferred requested pages into the second clock list upon achieving at least two consecutive cache hits of the transferred requested page; logging a history of pages evicted from the cache memory; and adaptively varying a proportion of pages marked as short and long-term utility to increase a cache hit ratio of the cache memory by utilizing the logged history of evicted pages.Type: ApplicationFiled: September 30, 2004Publication date: March 30, 2006Inventors: Sorav Bansal, Dharmendra Modha
-
Publication number: 20060069871Abstract: A self-tuning, low overhead, simple to implement, locally adaptive, novel cache management policy that dynamically and adaptively partitions the cache space amongst sequential and random streams so as to reduce read misses.Type: ApplicationFiled: September 30, 2004Publication date: March 30, 2006Inventors: Binny Gill, Dharmendra Modha
-
Publication number: 20050235114Abstract: An adaptive replacement cache policy dynamically maintains two lists of pages, a recency list and a frequency list, in addition to a cache directory. The policy keeps these two lists to roughly the same size, the cache size c. Together, the two lists remember twice the number of pages that would fit in the cache. At any time, the policy selects a variable number of the most recent pages to exclude from the two lists. The policy adaptively decides in response to an evolving workload how many top pages from each list to maintain in the cache at any given time. It achieves such online, on-the-fly adaptation by using a learning rule that allows the policy to track a workload quickly and effectively.Type: ApplicationFiled: June 13, 2005Publication date: October 20, 2005Inventors: Nimrod Megiddo, Dharmendra Modha
-
Publication number: 20050086436Abstract: A method for adaptively managing pages in a cache memory with a variable workload comprises defining a cache memory; organizing the cache into disjoint lists of pages, wherein the lists comprise lists T1, T2, B1, and B2; maintaining a bit that is set to either “S” or “L” for every page in the cache, which indicates whether the bit has short-term utility or long-term utility; ensuring that each member page of T1 is marked either as “S” or “L”, wherein each member page of T1 and B1 is marked as “S” and each member page of T2 and B2 is marked as “L”; and maintaining a temporal locality window parameter such that pages that are re-requested within a window are of short-term utility and pages that are re-requested outside the window are of long-term utility, wherein the cache comprises pages that are members of any of lists T1 and T2.Type: ApplicationFiled: October 21, 2003Publication date: April 21, 2005Inventor: Dharmendra Modha
-
Publication number: 20050071599Abstract: A method and system for dynamically allocating cache space in a storage system among multiple workload classes each having a unique set of quality-of-service (QoS) requirements. The invention dynamically adapts the space allocated to each class depending upon the observed response time for each class and the observed temporal locality in each class. The dynamic allocation is achieved by maintaining a history of recently evicted pages for each class, determining a future cache size for the class based on the history and the QoS requirements where the future cache size might be different than a current cache size for the class, determining whether the QoS requirements for the class are being met, and adjusting the future cache size to maximize the number of classes in which the QoS requirements are met. The future cache sizes are increased for the classes whose QoS requirements are not met while they are decreased for those whose QoS requirements are met.Type: ApplicationFiled: September 30, 2003Publication date: March 31, 2005Inventors: Dharmendra Modha, Divyesh Jadav, Pawan Goyal, Renu Tewari