Patents by Inventor Dharmendra Pandit

Dharmendra Pandit has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7994835
    Abstract: A duty control circuit including a clock input unit connected to a first node and a second node, the clock input unit receiving an input clock signal through the first node and changing a voltage of the second node to one of a first voltage level and a second voltage level in response to respective low and high logic levels of the input clock signal, a slew controller connected to the second node, the slew controller including one or more switches controlled by respective control signals, the one or more switches providing one of the first voltage level and the second voltage level to the second node in response to the control signals such that a slew rate of a signal at the second node is varied, and a clock output unit, the clock output unit outputting an output clock signal having a duty that varies.
    Type: Grant
    Filed: September 22, 2009
    Date of Patent: August 9, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwan-yeob Chae, Su-ho Kim, Won Lee, Sang-hoon Joo, Dharmendra Pandit, Jong-ryun Choi
  • Publication number: 20100073059
    Abstract: A duty control circuit including a clock input unit connected to a first node and a second node, the clock input unit receiving an input clock signal through the first node and changing a voltage of the second node to one of a first voltage level and a second voltage level in response to respective low and high logic levels of the input clock signal, a slew controller connected to the second node, the slew controller including one or more switches controlled by respective control signals, the one or more switches providing one of the first voltage level and the second voltage level to the second node in response to the control signals such that a slew rate of a signal at the second node is varied, and a clock output unit, the clock output unit outputting an output clock signal having a duty that varies.
    Type: Application
    Filed: September 22, 2009
    Publication date: March 25, 2010
    Inventors: Kwan-yeob Chae, Su-ho Kim, Won Lee, Sang-hoon Joo, Dharmendra Pandit, Jong-ryun Choi