Patents by Inventor Dharmendra THAKKAR

Dharmendra THAKKAR has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Posted interrupt processing in virtual machine monitor
    Patent number: 11080088
    Abstract: A processor includes a processor core, a processor cache to store reporting data structures including a queue structure, and an interrupt posting circuit coupled to the processor core and the processing cache. The interrupt posting circuit receives an interrupt request directed to a virtual processor (VP) of a virtual machine (VM) executed by the processor core. The VM is managed by a virtual machine monitor (VMM) executed by the processor core. The interrupt posting circuit determines the VP is in an inactive state and records the interrupt request in a first posted data structure allocated by the VMM for the VP in main memory coupled to the processor. The interrupt posting circuit updates location information stored in the reporting data structures based on recording the interrupt request in the first posted data structure to generate updated location information that identifies a location of the interrupt request.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: August 3, 2021
    Assignee: Intel Corporation
    Inventors: Arumugam Thiyagarajah, Rajesh Sankaran, Dharmendra Thakkar
  • POSTED INTERRUPT PROCESSING IN VIRTUAL MACHINE MONITOR
    Publication number: 20190121658
    Abstract: A processor includes a processor core, a processor cache to store reporting data structures including a queue structure, and an interrupt posting circuit coupled to the processor core and the processing cache. The interrupt posting circuit receives an interrupt request directed to a virtual processor (VP) of a virtual machine (VM) executed by the processor core. The VM is managed by a virtual machine monitor (VMM) executed by the processor core. The interrupt posting circuit determines the VP is in an inactive state and records the interrupt request in a first posted data structure allocated by the VMM for the VP in main memory coupled to the processor. The interrupt posting circuit updates location information stored in the reporting data structures based on recording the interrupt request in the first posted data structure to generate updated location information that identifies a location of the interrupt request.
    Type: Application
    Filed: December 19, 2018
    Publication date: April 25, 2019
    Inventors: Arumugam THIYAGARAJAH, Rajesh SANKARAN, Dharmendra THAKKAR