Patents by Inventor Dharmesh KUMAR
Dharmesh KUMAR has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11951457Abstract: Provided herein is a novel silica-supported nickel nanocomposite and a novel one-pot solution combustion synthesis of that nanocomposite. The method allows the synthesis of small size nickel nanoparticles (e.g., 3 nm to 40 nm) for which a considerable percentage of nickel is inserted into silica, experiencing strong metal-support interaction. These exceptional physicochemical properties make them desirable for various industrial applications, such as electronic, heterogeneous catalysis as well as conversion and storage of energy.Type: GrantFiled: January 4, 2022Date of Patent: April 9, 2024Inventors: Sardar Ali, Dharmesh Kumar, Ahmed Gamal, Mahmoud M. Khader, Muftah El-Naas
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Publication number: 20240027199Abstract: Aspects of the present disclosure provide methods, devices, and computer-readable storage media that support adaptive scheduling of electric vehicles (EVs) of an EV fleet for order deliveries. In some implementations, one or more aspects of the adaptive EV scheduling may be customized for EVs. For example, the adaptive EV scheduling may include identifying an energy efficient route that also reduces stress on a battery of an EV and may be based at least in part on a charging parameter associated with the EV. In some examples, the charging parameter may include one or more of a state of charge (SOC) associated with the battery, a state of health (SOH) associated with the battery, a location of a charging station for the EV, an average charging duration associated with the EV, or an intelligent charging parameter associated with the EV.Type: ApplicationFiled: December 14, 2022Publication date: January 25, 2024Inventors: Amit Kumar, Nishant Mehta, Piyush Manocha, Anshul Gupta, Naveen Sankaran, Anshul Anand, Sri Krishnan Narayanan, Dharmesh Kumar, Raffaele Menolascino
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Patent number: 11878287Abstract: This invention relates to development of novel Cu-based nanocatalysts synthesized via one-pot solution combustion synthesis for CO2 hydrogenation to methanol. The novel Cu-based catalyst has exceptional activity for CO2 hydrogenation with high methanol selectivity in the reaction temperature range between 250° C.-350° C. The novel catalyst also exhibits excellent resilience to deactivation due to sintering.Type: GrantFiled: January 7, 2022Date of Patent: January 23, 2024Assignee: QATAR UNIVERSITYInventors: Sardar Ali, Dharmesh Kumar, Muftah El-Naas
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Publication number: 20230072509Abstract: The present invention provides a method of preparing acetylene (C2H2), the method at least comprising the steps of: a) providing a methane-containing stream; b) subjecting the methane-containing stream provided in step a) to non-catalytic pyrolysis, thereby obtaining carbon and hydrogen; c) reacting the carbon obtained in step b) with CaO, thereby obtaining CaC2 and CO; d) reacting the CaC2 obtained in step c) with H2O, thereby obtaining acetylene (C2H2) and Ca(OH)2; e) decomposing the Ca(OH)2 obtained in step d), thereby obtaining CaO and H2O; f) using the CaO as obtained in step e) in the reaction of step c).Type: ApplicationFiled: February 16, 2021Publication date: March 9, 2023Inventors: Dharmesh KUMAR, Vikrant Nanasaheb URADE, Alexander Petrus VAN BAVEL, Alexander Willem VAN DER MADE
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Publication number: 20220219147Abstract: This invention relates to development of novel Cu-based nanocatalysts synthesized via one-pot solution combustion synthesis for CO2 hydrogenation to methanol. The novel Cu-based catalyst has exceptional activity for CO2 hydrogenation with high methanol selectivity in the reaction temperature range between 250° C.-350° C. The novel catalyst also exhibits excellent resilience to deactivation due to sintering.Type: ApplicationFiled: January 7, 2022Publication date: July 14, 2022Inventors: Sardar ALI, Dharmesh KUMAR, Muftah EL-NAAS
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Publication number: 20220212175Abstract: Provided herein is a novel silica-supported nickel nanocomposite and a novel one-pot solution combustion synthesis of that nanocomposite. The method allows the synthesis of small size nickel nanoparticles (e.g., 3 nm to 40 nm) for which a considerable percentage of nickel is inserted into silica, experiencing strong metal-support interaction. These exceptional physicochemical properties make them desirable for various industrial applications, such as electronic, heterogeneous catalysis as well as conversion and storage of energy.Type: ApplicationFiled: January 4, 2022Publication date: July 7, 2022Inventors: Sardar ALI, Dharmesh KUMAR, Ahmed GAMAL, Mahmoud M. KHADER, Muftah EL-NAAS
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Patent number: 11100087Abstract: A system to tokenize values may include a processing unit; a storage device comprising instructions, which when executed by the processing unit, configure the processing unit to: receive a data item with an original value from a first storage system; store the data item in a staging table; transform the original value of the data item in the staging table to a changed value based on a stored rule; store a mapping between the original value and the changed value in a library table; and transmit the library table to a second storage system configured to update a database table at the second storage system based on the library table.Type: GrantFiled: April 26, 2019Date of Patent: August 24, 2021Assignee: Microsoft Technology Licensing, LLCInventors: Shalini Gupta, Dharmesh Kumar, Elke Bregler, Rick Foucht, Navneet Saraogi, Frederic Huet, Ralph Yost, Gangaram Kanumuri
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Publication number: 20200341965Abstract: A system to tokenize values may include a processing unit; a storage device comprising instructions, which when executed by the processing unit, configure the processing unit to: receive a data item with an original value from a first storage system; store the data item in a staging table; transform the original value of the data item in the staging table to a changed value based on a stored rule; store a mapping between the original value and the changed value in a library table; and transmit the library table to a second storage system configured to update a database table at the second storage system based on the library table.Type: ApplicationFiled: April 26, 2019Publication date: October 29, 2020Inventors: Shalini Gupta, Dharmesh Kumar, Elke Bregler, Rick Foucht, Navneet Saraogi, Frederic Huet, Ralph Yost, Gangaram Kanumuri
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Patent number: 10544564Abstract: The present invention aims to improve the strength of the portion of the swing frame for attaching the swing motor apparatus while reducing cost. A bottom plate of a swing frame is divided into a center bottom plate segment to which the swing motor apparatus mounting portion is attached, a front bottom plate segment that is positioned to the front side of the center bottom plate segment and to which the center joint mounting portion is attached, and a rear bottom plate segment positioned to the rear side of the center bottom plate segment, wherein: the center, front, and rear bottom plate segments and are formed integrally by welding; and the plate thickness of the center bottom plate segment is thicker than the plate thickness of the front bottom plate segment and the rear bottom plate segment.Type: GrantFiled: May 12, 2017Date of Patent: January 28, 2020Assignee: Caterpillar SARLInventors: Takeshi Tsuneyoshi, Takahiro Iwamoto, Takeshi Nakamura, Akito Nakai, Kentaro Nakayama, Dharmesh Kumar, Koichi Andatsu
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Publication number: 20190153700Abstract: The present invention aims to improve the strength of the portion of the swing frame for attaching the swing motor apparatus while reducing cost. A bottom plate of a swing frame is divided into a center bottom plate segment to which the swing motor apparatus mounting portion is attached, a front bottom plate segment that is positioned to the front side of the center bottom plate segment and to which the center joint mounting portion is attached, and a rear bottom plate segment positioned to the rear side of the center bottom plate segment, wherein: the center, front, and rear bottom plate segments and are formed integrally by welding; and the plate thickness of the center bottom plate segment is thicker than the plate thickness of the front bottom plate segment and the rear bottom plate segment.Type: ApplicationFiled: May 12, 2017Publication date: May 23, 2019Applicant: Caterpillar SARLInventors: Takeshi Tsuneyoshi, Takahiro Iwamoto, Takeshi Nakamura, Akashi-shi Nakai, Kentaro Nakayama, Dharmesh Kumar, Koichi Andatsu
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Patent number: 9966131Abstract: A memory includes a memory cell that operates in response to an array supply voltage, and a corresponding pair of bit lines that are pre-charged to a periphery supply voltage prior to each access of the memory cell. A sense amplifier coupled to the bit lines operates in response to the periphery supply voltage. The periphery supply voltage is less than the array supply voltage to enable power savings within the memory. A first pair of transistors is configured to couple the sense amplifier to the bit lines during write accesses to the memory cell, thereby boosting the write voltages applied to the bit lines during a write operation. That is, the first pair of transistors is configured such that the sense amplifier pulls one of the bit lines toward the periphery supply voltage (and the other one of the bit lines toward the ground supply voltage) during write accesses.Type: GrantFiled: August 21, 2015Date of Patent: May 8, 2018Assignee: Synopsys, Inc.Inventors: Dharmesh Kumar Sonkar, Niranjan Behera
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Patent number: 9865334Abstract: A voltage supply circuit for a memory cell including a first circuit coupled between a first voltage supply and a first voltage supply terminal of the memory cell, and a second circuit coupled between the first voltage supply and a second voltage supply terminal of the memory cell. The first circuit is controlled by a first bit line of the memory cell, and the second circuit is controlled by a second bit line of the memory cell. The first and second circuits provide the first supply voltage to the first and second voltage supply terminals of the memory cell, respectively, during a pre-charge phase. During a write operation, only one of the first circuit and the second circuit provides the first supply voltage to the memory cell, and the other one of the first circuit and the second circuit provides an adjusted voltage (e.g., a collapsed voltage) to the memory cell.Type: GrantFiled: December 2, 2016Date of Patent: January 9, 2018Assignee: Synopsys, Inc.Inventor: Dharmesh Kumar Sonkar
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Publication number: 20170369976Abstract: The present invention disclosed an ultra-high strength steel for structural components, a process of making such steel that has a desirable microstructure in the thermo-mechanically processed and differently cooled conditions that delivers high fatigue performance in service, and a process of making forged components using such steel. The steel and the process of its manufacturing enables manufacture of components that exhibit bainitic microstructure that impart ultra-high strength ranges with very high fatigue performance. The invention enables saving in alloying additives compared to hardened and tempered alloy steels and in addition avoid expensive heat treatment operations to achieve the desired range of mechanical properties. The steel of the invention is a suitable replacement for micro alloyed steel or heat treated steel bars used for structural component development.Type: ApplicationFiled: October 21, 2015Publication date: December 28, 2017Applicants: BHARAT FORGE LIMITED, Kalyani Carpenter Special Steels LimitedInventors: Babasaheb Neelkanth Kalyani, Madan Umakant Takale, Prakasam Balachandran Gnana, Rajkumar Prasad Singh, Abhay Ramchandra Chauthai, Suresh Babu Arangi, Rajesh Surendra Mane, Dharmesh Kumar, Srinivas Perla, Vinayak Pralhad Pawar, Shital Shahaji Jadhav
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Publication number: 20170243635Abstract: A voltage supply circuit for a memory cell including a first circuit coupled between a first voltage supply and a first voltage supply terminal of the memory cell, and a second circuit coupled between the first voltage supply and a second voltage supply terminal of the memory cell. The first circuit is controlled by a first bit line of the memory cell, and the second circuit is controlled by a second bit line of the memory cell. The first and second circuits provide the first supply voltage to the first and second voltage supply terminals of the memory cell, respectively, during a pre-charge phase. During a write operation, only one of the first circuit and the second circuit provides the first supply voltage to the memory cell, and the other one of the first circuit and the second circuit provides an adjusted voltage (e.g., a collapsed voltage) to the memory cell.Type: ApplicationFiled: December 2, 2016Publication date: August 24, 2017Inventor: Dharmesh Kumar Sonkar
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Publication number: 20170053695Abstract: A memory includes a memory cell that operates in response to an array supply voltage, and a corresponding pair of bit lines that are pre-charged to a periphery supply voltage prior to each access of the memory cell. A sense amplifier coupled to the bit lines operates in response to the periphery supply voltage. The periphery supply voltage is less than the array supply voltage to enable power savings within the memory. A first pair of transistors is configured to couple the sense amplifier to the bit lines during write accesses to the memory cell, thereby boosting the write voltages applied to the bit lines during a write operation. That is, the first pair of transistors is configured such that the sense amplifier pulls one of the bit lines toward the periphery supply voltage (and the other one of the bit lines toward the ground supply voltage) during write accesses.Type: ApplicationFiled: August 21, 2015Publication date: February 23, 2017Inventors: Dharmesh Kumar Sonkar, Niranjan Behera
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Publication number: 20160237005Abstract: The present invention provides a process for the oxidative dehydrogenation of ethane to ethylene, the process at least comprising the steps of: (a) providing an ethane-containing stream (10); (b) subjecting the ethane-containing stream (10) provided in step (a) to oxidative dehydrogenation, thereby obtaining a stream (20) containing at least ethylene, water and acetic acid; (c) separating acetic acid from the stream (20) obtained in step (b), thereby obtaining a concentrated acetic acid stream (60) and a first ethylene-enriched stream (40); (d) subjecting the concentrated acetic acid stream (60) obtained in step (c) to hydrogenation thereby obtaining an ethanol-containing stream (80); and (e) subjecting the ethanol-containing stream (80) obtained in step (d) to dehydration thereby obtaining a second ethylene-enriched stream (90).Type: ApplicationFiled: October 24, 2014Publication date: August 18, 2016Inventors: Dharmesh KUMAR, Ronald Jan SCHOONEBEEK
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Publication number: 20130106498Abstract: Circuits, and methods for reducing standby leakage power in Integrated Circuit (ICs) are disclosed. In an embodiment, an IC includes a core circuit, a first switch and a second switch, where the first switch is coupled between a power terminal of the core circuit and a power supply and the second switch is coupled between a ground terminal of the core circuit and a ground supply. The first switch and the second switch are configured to power ON and OFF the core circuit. The IC includes a first feedback circuit configured to control ON and OFF states of the first switch based on voltage at the power terminal, and a second feedback circuit configured to control ON and OFF states of the second switch based on voltage at the ground terminal of the core circuit during the standby mode for maintaining the logic state of the core circuit.Type: ApplicationFiled: October 26, 2011Publication date: May 2, 2013Applicant: Texas Instruments IncorporatedInventors: Dharmesh Kumar Sonkar, Shahid Ali
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Patent number: 8416013Abstract: Circuits, and methods for reducing standby leakage power in Integrated Circuit (ICs) are disclosed. In an embodiment, an IC includes a core circuit, a first switch and a second switch, where the first switch is coupled between a power terminal of the core circuit and a power supply and the second switch is coupled between a ground terminal of the core circuit and a ground supply. The first switch and the second switch are configured to power ON and OFF the core circuit. The IC includes a first feedback circuit configured to control ON and OFF states of the first switch based on voltage at the power terminal, and a second feedback circuit configured to control ON and OFF states of the second switch based on voltage at the ground terminal of the core circuit during the standby mode for maintaining the logic state of the core circuit.Type: GrantFiled: October 26, 2011Date of Patent: April 9, 2013Assignee: Texas Instruments IncorporatedInventors: Dharmesh Kumar Sonkar, Shahid Ali
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Publication number: 20120321896Abstract: The present invention provides particulate rasagiline mesylate having a particle size of about 255 microns to about 590 microns. Particularly it relates to a process of preparing rasagiline mesylate having large particle size by crystallisation techniques and devoid of comminution techniques to control particle size.Type: ApplicationFiled: January 28, 2011Publication date: December 20, 2012Inventors: Kuppuswamy Nagarajan, Rajiv Kumar, Dharmesh Kumar Arvindbhai Patel, Jaman Mandaviya
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Publication number: 20120259116Abstract: The present invention relates to a novel process for the preparation of paliperidone by hydrolysis of 9-O-acylated paliperidone. In a preferred embodiment of the present invention, Paliperidone Form (II) of purity of about 98% or more was obtained by basic hydrolysis of 9-O-Acetyl Paliperidone.Type: ApplicationFiled: December 20, 2010Publication date: October 11, 2012Inventors: Rajiv Kumar, Dharmesh Kumar Arvindbhaipatel, Dattatray Shamrao Metil, Praveen Raosaheb Supekar, Prashant Pandurangpawar, Santosh Vitthal Pune