Abstract: Various embodiments include methods and devices for portion interleaving for asymmetric size memory portions. Embodiments may include determining an asymmetric memory portion assignment for an interleave unit, determining a consumed address space offset for consumed address space of a memory, modifying an address of the interleave unit using the consumed address space offset, and assigning the interleave unit to an interleave granule in the asymmetric memory portion using the modified address in a compact manner before assigning another interleave unit to another interleave granule. Embodiments may include receiving an address of memory access request in a memory, mapping the address to an interleave granule in an asymmetric memory portion, assigning consecutive interleave units to the interleave granule while the interleave granule has unused space before assigning another interleave unit to another interleave granule, and implementing the memory access request at the mapped address.

Abstract: Various embodiments include methods and devices for portion interleaving for asymmetric size memory portions. Embodiments may include determining an asymmetric memory portion assignment for an interleave unit, determining a consumed address space offset for consumed address space of a memory, modifying an address of the interleave unit using the consumed address space offset, and assigning the interleave unit to an interleave granule in the asymmetric memory portion using the modified address in a compact manner before assigning another interleave unit to another interleave granule. Embodiments may include receiving an address of memory access request in a memory, mapping the address to an interleave granule in an asymmetric memory portion, assigning consecutive interleave units to the interleave granule while the interleave granule has unused space before assigning another interleave unit to another interleave granule, and implementing the memory access request at the mapped address.

Abstract: Various embodiments include methods and devices for portion interleaving for asymmetric size memory portions. Embodiments may include determining an asymmetric memory portion assignment for an interleave unit, determining a consumed address space offset for consumed address space of a memory, modifying an address of the interleave unit using the consumed address space offset, and assigning the interleave unit to an interleave granule in the asymmetric memory portion using the modified address in a compact manner before assigning another interleave unit to another interleave granule. Embodiments may include receiving an address of memory access request in a memory, mapping the address to an interleave granule in an asymmetric memory portion, assigning consecutive interleave units to the interleave granule while the interleave granule has unused space before assigning another interleave unit to another interleave granule, and implementing the memory access request at the mapped address.

Abstract: A system, method, and computer program product are provided herein to manage DRAM bank activation per cycle. A memory controller with embedded scheduling logic is employed to manage the system, method, and computer program product and to restrict the quantity of active banks in a given cycle, resulting in power savings with minimal performance loss, if any. The scheduling logic provides instructions to manage the state of associated DRAM banks. Each bank is either in an idle state or an active state, with the idle state consuming less power than the active state. The scheduling logic restricts the quantity of active banks in any cycle, with all other banks being in an idle state, which provides power savings to the associated system.

Abstract: A system, method, and computer program product are provided herein to manage DRAM bank activation per cycle. A memory controller with embedded scheduling logic is employed to manage the system, method, and computer program product and to restrict the quantity of active banks in a given cycle, resulting in power savings with minimal performance loss, if any. The scheduling logic provides instructions to manage the state of associated DRAM banks. Each bank is either in an idle state or an active state, with the idle state consuming less power than the active state. The scheduling logic restricts the quantity of active banks in any cycle, with all other banks being in an idle state, which provides power savings to the associated system.

Abstract: A system, method, and computer program product are provided herein to manage DRAM bank activation per cycle. A memory controller with embedded scheduling logic is employed to manage the system, method, and computer program product and to restrict the quantity of active banks in a given cycle, resulting in power savings with minimal performance loss, if any. The scheduling logic provides instructions to manage the state of associated DRAM banks. Each bank is either in an idle state or an active state, with the idle state consuming less power than the active state. The scheduling logic restricts the quantity of active banks in any cycle, with all other banks being in an idle state, which provides power savings to the associated system.

Abstract: Scheduling memory operations using bank groups including receiving, by a sequencing engine in a memory controller, a set of operations targeting locations in a memory device, wherein the memory device comprises a plurality of bank groups; determining, by the sequencing engine, a targeted bank group of each of the set of operations; selecting, by the sequencing engine, one of the set of operations based on the targeted bank group of each of the set of operations and a bank group of a previously sent operation; and sending, by the sequencing engine, the selected one of the set of operations to the memory device.

Abstract: A system, method, and computer program product are provided herein to manage DRAM bank activation per cycle. A memory controller with embedded scheduling logic is employed to manage the system, method, and computer program product and to restrict the quantity of active banks in a given cycle, resulting in power savings with minimal performance loss, if any. The scheduling logic provides instructions to manage the state of associated DRAM banks. Each bank is either in an idle state or an active state, with the idle state consuming less power than the active state. The scheduling logic restricts the quantity of active banks in any cycle, with all other banks being in an idle state, which provides power savings to the associated system.

Abstract: Scheduling memory operations using bank groups including receiving, by a sequencing engine in a memory controller, a set of operations targeting locations in a memory device, wherein the memory device comprises a plurality of bank groups; determining, by the sequencing engine, a targeted bank group of each of the set of operations; selecting, by the sequencing engine, one of the set of operations based on the targeted bank group of each of the set of operations and a bank group of a previously sent operation; and sending, by the sequencing engine, the selected one of the set of operations to the memory device.

Abstract: A computer system has a plurality of processors with non-blocking memory caches. A controller sets an upper limit of allowed snoop commands for the computer system. The controller adjusts, using real-time bandwidth data of the computing system, the limit of snoop commands to a new numerical value. The controller detects that the snoop limit is being adjusted between snoop rates more than a threshold number of times. The controller designates an overriding limit of snoop commands in response to detecting the snoop limit being adjusted more than the threshold number of times. The overriding limit of snoop commands is fixed for a period of time. The controller delays snoop commands which exceed the overriding limit of snoop commands during the period of time.

Abstract: A computer system has a plurality of processors with non-blocking memory caches. A controller sets an upper limit of allowed snoop commands for the computer system. The controller adjusts, using real-time bandwidth data of the computing system, the limit of snoop commands to a new numerical value. The controller detects that the snoop limit is being adjusted between snoop rates more than a threshold number of times. The controller designates an overriding limit of snoop commands in response to detecting the snoop limit being adjusted more than the threshold number of times. The overriding limit of snoop commands is fixed for a period of time. The controller delays snoop commands which exceed the overriding limit of snoop commands during the period of time.

Abstract: A computer system has a plurality of processors with non-blocking memory caches. A controller sets an upper limit of allowed snoop commands for the computer system. The controller adjusts, using real-time bandwidth data of the computing system, the limit of snoop commands to a new numerical value. The controller detects that the snoop limit is being adjusted between snoop rates more than a threshold number of times. The controller designates an overriding limit of snoop commands in response to detecting the snoop limit being adjusted more than the threshold number of times. The overriding limit of snoop commands is fixed for a period of time. The controller delays snoop commands which exceed the overriding limit of snoop commands during the period of time.

Abstract: A computer system has a plurality of processors with non-blocking memory caches. A controller sets an upper limit of allowed snoop commands for the computer system. The controller adjusts, using real-time bandwidth data of the computing system, the limit of snoop commands to a new numerical value. The controller detects that the snoop limit is being adjusted between snoop rates more than a threshold number of times. The controller designates an overriding limit of snoop commands in response to detecting the snoop limit being adjusted more than the threshold number of times. The overriding limit of snoop commands is fixed for a period of time. The controller delays snoop commands which exceed the overriding limit of snoop commands during the period of time.

Abstract: The invention is directed to techniques for processing order messages exchanged between a client and an order server. The order messages can be for products and services that the customer orders from a vendor. The client provides the input order messages, which contain order commands in a predefined document format, to an order message manager of the order server, which also provides an order message sorter and message processing modules. The order message sorter reads the input document in the input order message to determine a type for the message and then directs the message to a message processing module capable of processing that type of order message. The message processing module processes the input document, obtains data if needed from an order database, and prepares an output document to include in an output order message to be returned to the client.

Abstract: The invention is directed to techniques for processing order messages exchanged between a client and an order server. The order messages can be for products and services that the customer orders from a vendor. The client provides the input order messages, which contain order commands in a predefined document format, to an order message manager of the order server, which also provides an order message sorter and message processing modules. The order message sorter reads the input document in the input order message to determine a type for the message and then directs the message to a message processing module capable of processing that type of order message. The message processing module processes the input document, obtains data if needed from an order database, and prepares an output document to include in an output order message to be returned to the client.

Abstract: The invention is directed to techniques for processing order messages exchanged between a client and an order server. The order messages can be for products and services that the customer orders from a vendor. The client provides the input order messages, which contain order commands in a predefined document format, to an order message manager of the order server, which also provides an order message sorter and message processing modules. The order message sorter reads the input document in the input order message to determine a type for the message and then directs the message to a message processing module capable of processing that type of order message. The message processing module processes the input document, obtains data if needed from an order database, and prepares an output document to include in an output order message to be returned to the client.

Abstract: The invention is directed to techniques for processing order messages exchanged between a client and an order server. The order messages can be for products and services that the customer orders from a vendor. The client provides the input order messages, which contain order commands in a predefined document format, to an order message manager of the order server, which also provides an order message sorter and message processing modules. The order message sorter reads the input document in the input order message to determine a type for the message and then directs the message to a message processing module capable of processing that type of order message. The message processing module processes the input document, obtains data if needed from an order database, and prepares an output document to include in an output order message to be returned to the client.