Patents by Inventor Dharmesh Tirthdasani

Dharmesh Tirthdasani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Power gated memory device with power state indication
    Patent number: 8947966
    Abstract: A memory device comprises one or more power gates and state signaling circuitry. Each of the one or more power gates is configurable such that a respective portion of the memory device is powered down. The state signaling circuitry is operative to produce a power state output signal indicative of when the one or more power gates are configured such that the memory device is fully powered up.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: February 3, 2015
    Assignee: LSI Corporation
    Inventors: Sathappan Palaniappan, Romeshkumar Mehta, Dharmesh Tirthdasani
  • POWER-GATED MEMORY DEVICE WITH POWER STATE INDICATION
    Publication number: 20130332763
    Abstract: A memory device comprises one or more power gates and state signaling circuitry. Each of the one or more power gates is configurable such that a respective portion of the memory device is powered down. The state signaling circuitry is operative to produce a power state output signal indicative of when the one or more power gates are configured such that the memory device is fully powered up.
    Type: Application
    Filed: June 11, 2012
    Publication date: December 12, 2013
    Applicant: LSI CORPORATION
    Inventors: Sathappan Palaniappan, Romeshkumar Mehta, Dharmesh Tirthdasani