Abstract: The drain bit line capacitance of a segmented alternate-metal virtual-ground (AMG) flash memory array is reduced by connecting the virtual or noncontinuous bit lines of the array to a drain voltage via select transistors that are not connected to the continuous bit lines that extend through each of the segments of the array.

Abstract: An EPROM memory array and method of controlling the array. The array is divided into array segments, with each segment having alternating bit and source lines. Each segment includes several rows of cells, with each cell in the row having a control gate connected to the word line, a drain connected to one of the bit lines and a source connected to the source line adjacent the bit line. Pairs of cells in a row will have common sources connected to one of the source lines and respective drains connected to the two bit lines adjacent the source line. A selected cell is read utilizing a pair of segment select transistors which selectively connect a positive voltage to the bit line connected to the drain of the selected cell, with the source of the cell being grounded. The bit lines connected to the drains are thus selectively accessible and isolatable so that they need extend over only a single segment of the array.

Abstract: A non-volatile memory system which includes an array of memory cells with each of the cells including a source, drain and intermediate channel and which is suitable for low voltage operation such as battery powered applications. A floating gate is positioned over the channel and a control gate is positioned over the floating gate. The array is formed in a P type well, with the P well being formed in an N type well. The N well is formed in a P type substrate. The system includes circuitry for applying appropriate voltages for programming selected cells, reading selected cells and erasing the cells. The substrate is biased to circuit ground and, in read operations, the N well/P well PN junction is reversed biased. A positive voltage, typically a low level battery-supplied voltage, is applied to the control gate of the selected cell to be read and the source of the selected cell is biased to a negative voltage.

Abstract: A semiconductor flash memory cell which includes a P type substrate with an N type well formed therein followed by a P type well formed within the N well. An N type drain is formed in the P well as is an N type source, with the drain and source being spaced apart so as to create a channel region therebetween. A floating gate is disposed over only a part of the channel and a first segment of a control gate is disposed over the remainder of the channel. A second segment of the control gate is disposed over the floating gate. The arrangement of the floating and control gate functions to eliminate adverse effects of over erase. In addition, the well-within-a-well structure enables biasing voltages to be applied during erase which forces electrons removed from the floating gate to enter the channel region, rather than the drain region thereby increasing the program/erase cycle endurance of the cell.

Abstract: An Electrically Programmable Read Only Memory (EPROM) memory cell includes a serially connected Complementary Metal Oxide Silicon (CMOS) transistor pair having common floating gates and common control gates. A third n-type floating gate field effect transistor is utilized for programming the memory cell. The floating gate and the control gate of the third transistor are connected to the common floating gates and the common control gates, respectively, of the Complementary Metal Oxide Silicon (CMOS) transistor pair. The memory cell is tri-statable by connecting the source of the p-channel transistor of the Complementary Metal Oxide Silicon (CMOS) pair to the common control gates.

Abstract: A CMOS ring oscillator includes an odd number of serially connected inverter stages with each stage comprising a CMOS transistor pair. The output of each stage is taken at the common terminal of the CMOS transistor pair with capacitive means shunting the output of each stage to circuit ground. The input of each stage is applied at the gate of the p-channel transistor. A fixed reference voltage, V.sub.REF, is applied to the gate of each n-channel transistor, whereby the discharge of voltage on the capacitive means through the n-channel transistor is independent of supply voltage.

Abstract: A programmable memory cell useful in a logic cell array draws no D.C. power in either a "1" or a "0" state. The cell includes a CMOS transistor pair including a p-channel transistor connected to a positive voltage source and an n-channel transistor connected to a circuit ground potential. The cell output is connected to a common terminal of the CMOS transistor pair. The CMOS transistor pair has a common floating gate which is selectively charged for programming the cell. In a preferred embodiment, the floating gate comprises a first polycrystalline silicon layer (polysilicon), and capacitive means including a second polysilicon layer spaced from and capacitively coupled with the first polysilicon layer is utilized to selectively applying charge to the common floating gate.

Abstract: An EEPROM or EPPROM programming switch operable at low circuit voltage (V.sub.CC) includes a first pair of native field effect transistors interconnected between a word line and a programming voltage potential and a second pair of serially connected native transistor devices connected between a charge pump node and the programming voltage. The gate electrodes of the first pair of transistors are connected to the charge pump node and the gate electrodes of the second pair of transistors are connected to the word line. Decoding means is provided for preventing charge accumulation of the word line when the word line is not selected and for permitting charge accumulation of the word line when the word line is selected for programming. The common terminals of the first and second transistors and the third and fourth transistors are connected to a bias circuit for preventing conduction of the transistors when the word line has not been selected for programming.

Abstract: An EEPROM programming switch includes a first enhancement mode field effect transistor interconnected between a word line and a programming voltage potential, and a second enhancement mode field effect transistor connected between a charge pump node and the programming voltage. The gate electrode of the first transistor is connected to the charge pump node and the gate electrode of the second transistor is connected to the word line. Decoding means is providing for preventing charge accumulation of the word line when the word line is not selected and for permitting charge accumulation of the word line when the word line is selected for programming.

Abstract: An electrically erasable, programmable read-only-memory cell compatible with a high voltage value generator for writing and erasing in the cell being in the same chip.

Abstract: A system is disclosed to charge an output region to a selected voltage in a series of steps, each step raising the voltage of the output region by an amount less than the desired final voltage level. A portion of the system having a control terminal causes the voltage at the output region to increase by a step in response to a change in electrical conditions on the control terminal. Another portion of the system maintains electrical conditions at the pull up means control terminating region between steps. A further portion of the system is also provided to maintain electrical conditions at the control terminal at a level which will prevent the output region voltage from increasing when such an elevated voltage on the output region is undesired.