Abstract: In some aspects, the present disclosure provides a method for generating a frame. The method includes receiving a first fence indicating that a first frame stored in a display processor unit (DPU) buffer has been consumed by a hardware component. The method also includes in response to receiving the first fence, fetching a plurality of layers from an application buffer, the plurality of layers corresponding to a second frame. The method also includes determining to use both a DPU and a graphics processing unit (GPU) to process the plurality of layers for composition of the second frame. The method also includes fetching the first fence from the DPU buffer and generating a second fence.

Abstract: The present disclosure relates to methods and apparatus for display processing. The apparatus can calculate a bandwidth compression ratio (CR) for each of a plurality of tile rows in one or more layers in a frame, each of the one or more layers being associated with one or more regions in the frame. The apparatus can also determine a bandwidth CR for each of the one or more regions associated with each of the one or more layers based on the calculated bandwidth CR for the plurality of tile rows in the one or more layers. Additionally, the apparatus can determine a total bandwidth for the frame based on the determined bandwidth CR for each of the one or more regions associated with the one or more layers. The apparatus can also calculate a total bandwidth for each of the one or more regions.

Abstract: Methods, systems, and devices for image processing are described. A device may determine one or more static layers of a layer stack and one or more updating layers of the layer stack. The device may determine an order of the one or more static layers, or the one or more updating layers, or both in the layer stack. In some examples, the device may modify the order in the layer stack by positioning the one or more static layers below the one or more updating layers in the layer stack. Each static layer of the one or more static layers may be associated with a first blending equation and each updating layer of the one or more updating layers may be associated with a second blending equation. As a result, the device may process the layer stack based on the modified order.

Abstract: In some aspects, the present disclosure provides a method for bandgap voting. In some configurations, the method includes receiving, at a hardware voting component associated with a destination subsystem, metadata for each of a plurality of compressed display tiles, wherein for each of the plurality of compressed display tiles the metadata indicates an amount of compression of the compressed display tile. In some configurations, the method includes dividing the plurality of compressed display tiles into a plurality of sets of compressed display tiles. In some configurations, for each of the plurality of sets of compressed display tiles, the method includes determining a desired bandwidth for communicating the set of compressed display tiles over a bus, and receiving the set of compressed display tiles at the destination subsystem over the bus at an actual bandwidth that is based on the desired bandwidth.

Abstract: In some aspects, the present disclosure provides a method for bandgap voting. In some configurations, the method includes receiving, at a hardware voting component associated with a destination subsystem, metadata for each of a plurality of compressed display tiles, wherein for each of the plurality of compressed display tiles the metadata indicates an amount of compression of the compressed display tile. In some configurations, the method includes dividing the plurality of compressed display tiles into a plurality of sets of compressed display tiles. In some configurations, for each of the plurality of sets of compressed display tiles, the method includes determining a desired bandwidth for communicating the set of compressed display tiles over a bus, and receiving the set of compressed display tiles at the destination subsystem over the bus at an actual bandwidth that is based on the desired bandwidth.

Abstract: An improved method and system for power-efficient display are provided. Burst mode display processing allows a host processor to compose and render multiple low-resolution frames in a computation cycle. The low-resolution frames are transferred to a display panel, and the host processor enters a power-saving mode and minimizes power consumption while the frames are being displayed. In one embodiment, the host processor drives frame switches at the display panel while in a power-saving mode. In another embodiment, the display panel drives frame switches itself with no further input from the host processor.

Abstract: According to various aspects, just-in-time system bandwidth changes may be implemented in hardware to optimize power consumption and performance in an electronic device. More particularly, in a periodic system associated with an electronic device, a bandwidth for a next frame may be configured during a current frame via software operating on the electronic device. Hardware associated with the periodic system may issue a bandwidth change request for the next frame when a current time reaches a bandwidth increase threshold in response to actual processing time associated with the current frame finishing prior to the bandwidth increase threshold, which may be defined relative to a timer deadline that defines when the next frame starts to process.

Abstract: Methods, systems, and devices for processing display data are described. A device may receive a bitstream sequence including a quantity of intra-coded frames, inter-coded frames, or bi-directional frames, or a combination thereof. In some examples, the device may be a decoding device or an encoding device. Upon receiving the bitstream sequence, the device may determine a refresh pixel region for a frame based on an order of the quantity of intra-coded frames, inter-coded frames, or bi-directional frames, or a combination thereof. In some examples, the order may be an encoding order of the intra-coded frames, inter-coded frames, or bi-directional frames, or a combination thereof. The device may then send the refresh pixel region for the frame to a display device based on determining the refresh pixel region for the frame.

Abstract: The present disclosure relates to methods and apparatus for video processing. Aspects of the present disclosure can identify one or more macroblocks (MBs) in a frame including a static luminance. In some aspects, the static luminance can be a luminance value that is static for a time period. Aspects of the present disclosure can also determine whether at least one MB of the one or more MBs includes the static luminance for a time period greater than or equal or a luminance threshold duration. Also, the present disclosure can adjust the luminance value of the at least one MB based on the determination whether the at least one MB includes the static luminance for a time period greater than or equal or the luminance threshold duration. Further, the present disclosure can store, as static luminance information, the determination whether the at least one MB includes the static luminance.

Abstract: Methods, systems, and devices for processing display data are described. A device may receive a bitstream sequence including a quantity of intra-coded frames, inter-coded frames, or bi-directional frames, or a combination thereof. In some examples, the device may be a decoding device or an encoding device. Upon receiving the bitstream sequence, the device may determine a refresh pixel region for a frame based on an order of the quantity of intra-coded frames, inter-coded frames, or bi-directional frames, or a combination thereof. In some examples, the order may be an encoding order of the intra-coded frames, inter-coded frames, or bi-directional frames, or a combination thereof. The device may then send the refresh pixel region for the frame to a display device based on determining the refresh pixel region for the frame.

Abstract: According to various aspects, just-in-time system bandwidth changes may be implemented in hardware to optimize power consumption and performance in an electronic device. More particularly, in a periodic system associated with an electronic device, a bandwidth for a next frame may be configured during a current frame via software operating on the electronic device. Hardware associated with the periodic system may issue a bandwidth change request for the next frame when a current time reaches a bandwidth increase threshold in response to actual processing time associated with the current frame finishing prior to the bandwidth increase threshold, which may be defined relative to a timer deadline that defines when the next frame starts to process.

Abstract: The disclosure relates to a system including a set of subsystems sharing a voltage rail. The system includes a power controller configured to send messages, such as interrupts, to the subsystems concerning a change of state of a supply voltage on the voltage rail. Such messages may have been sent in response to requests and messages from the subsystems, respectively. In response to the messages, the subsystems may send requests to the power controller for different dynamic clock voltage scaling (DCVS) levels, respectively. In response to such requests, the power controller may set the supply voltage and frequencies of clock signals for the requesting subsystems, respectively.

Abstract: The disclosure relates to a system including a set of subsystems sharing a voltage rail. The system includes a power controller configured to send messages, such as interrupts, to the subsystems concerning a change of state of a supply voltage on the voltage rail. Such messages may have been sent in response to requests and messages from the subsystems, respectively. In response to the messages, the subsystems may send requests to the power controller for different dynamic clock voltage scaling (DCVS) levels, respectively. In response to such requests, the power controller may set the supply voltage and frequencies of clock signals for the requesting subsystems, respectively.