Abstract: A switchable bias current biases, in an operational state, a differential amplifier with a full-slew bias current. A system on/off signal transitions from an operational state to a power-down state. The transition disables the differential amplifier and switches the switchable bias current to a reduced slew bias current. The system on/off signal transitions from the power-down state to the operational state, the differential amplifier is enabled, and the switchable bias current is delayed, by a reduced slew duration, from switching to the full-slew bias current. The enabled differential amplifier slews toward a reference voltage at a reduced slew rate caused by the reduced slew bias current. The switchable bias current, after the reduced slew duration, switches to the full-slew bias current. Optionally, a regulated pass gate is disabled in response to the system on/off signal transitioning from the operational state to the power-down state.

Abstract: An adaptive low dropout (LDO) regulator includes a load-based bias controller that generates a bias control signal based on the output load current, and has a differential amplifier with a bias adjustment that receives the bias control signal and responds by adjusting a bias of a transistor within the adaptive LOD regulator. Optionally, the bias control signal is generated according to a hysteresis rule. Optionally, the adaptive LOD regulator includes an adaptive load-based compensation network having a zero, the zero having a location based, at least in part, one more of an adjustable resistance or capacitance value controlled by the load-based bias controller.

Abstract: A transient response accelerated (TRA) low dropout (LDO) regulator has an error amplifier having a feedback input, and a reference input configured to receive a reference voltage, and an output that controls a pass gate. The pass gate output voltage is applied to the feedback input. A transient response accelerator (TRA) circuit detects a rapid voltage drop on the pass gate output and, in response, applies a pulse control that rapidly lowers the resistance of the pass gate.

Abstract: Methods and apparatus for a successive approximation register analog to digital converter are provided. In an example, provided is a method for digitally representing an analog input signal. A bit of the digital output signal is generated by altering a test voltage by an amount comparable to a weight afforded to the bit, comparing the altered test voltage with the analog input signal to create a comparison output, switching a two-to-one multiplexer to select the comparison output instead of a preceding shift-successive approximation register block output, storing the comparison output in a flip-flop, inhibiting clocking of the flip-flop, and outputting the comparison output from the flip-flop as the bit of the digital output signal.

Abstract: A bypass low dropout regulator has a pass gate coupled to a voltage rail. The pass gate receives a pass gate control signal on a pass gate control line and controllably drops a voltage from a rail to a regulated output in accordance with the pass gate control signal. A differential amplifier generates the pass gate control voltage using a reference and feedback from the regulated output. A bypass switch selectively bypasses the regulator control signal, in response to a bypass signal, by placing a pass gate ON voltage on the pass gate control line. Optionally, and ON-OFF mode circuit selectively disables the pass gate in response to a system ON-OFF signal.

Abstract: Polarity compensating dual-string digital-to-analog converters (DACs), and related circuits, systems, and methods are disclosed. In embodiments disclosed herein, a secondary voltage divider of a dual-string DAC includes a switch logic unit. The switch logic unit is configured to compensate for polarity changes in the dual-string DAC to maintain monotonicity. Monotonicity means an output voltage of a DAC either increases or stays constant for monotonically increasing functions or either decreases or stays constant for monotonically decreasing functions given an incremental change in a DAC input code. The switch logic unit is configured to compensate for polarity changes in the input voltage from the primary voltage divider to the secondary resistor string. The switch logic unit is configured to select a secondary switch among the plurality of secondary switches in a secondary voltage divider, to divide an input voltage based on a polarity indicator and a DAC input code, to maintain monotonicity.

Abstract: Dual-string digital-to-analog converters (DACs), and related circuits, systems, and methods are disclosed. In embodiments disclosed herein, a primary voltage divider of the dual string-DAC is comprised of at least one adjusting circuit. The adjusting circuit is configured to maintain the ideal voltage of a selected resistor node pair across a secondary voltage divider circuit in response to a primary switch unit selecting a selected resistor node pair. In this manner, impedance isolation is not required between a primary voltage divider and the secondary voltage divider circuit of the dual-string DAC. As a result, as non-limiting examples, the area on an integrated circuit (IC) for a dual-string DAC may be decreased, power consumption of the DAC may be decreased, and/or the dual-string DAC may have increased performance by not requiring a settling time.

Abstract: Dual-string digital-to-analog converters (DACs), and related circuits, systems, and methods are disclosed. In embodiments disclosed herein, a primary voltage divider of the dual string-DAC is comprised of at least one adjusting circuit. The adjusting circuit is configured to maintain the ideal voltage of a selected resistor node pair across a secondary voltage divider circuit in response to a primary switch unit selecting a selected resistor node pair. In this manner, impedance isolation is not required between a primary voltage divider and the secondary voltage divider circuit of the dual-string DAC. As a result, as non-limiting examples, the area on an integrated circuit (IC) for a dual-string DAC may be decreased, power consumption of the DAC may be decreased, and/or the dual-string DAC may have increased performance by not requiring a settling time.

Abstract: Polarity compensating dual-string digital-to-analog converters (DACs), and related circuits, systems, and methods are disclosed. In embodiments disclosed herein, a secondary voltage divider of a dual-string DAC includes a switch logic unit. The switch logic unit is configured to compensate for polarity changes in the dual-string DAC to maintain monotonicity. Monotonicity means an output voltage of a DAC either increases or stays constant for monotonically increasing functions or either decreases or stays constant for monotonically decreasing functions given an incremental change in a DAC input code. The switch logic unit is configured to compensate for polarity changes in the input voltage from the primary voltage divider to the secondary resistor string. The switch logic unit is configured to select a secondary switch among the plurality of secondary switches in a secondary voltage divider, to divide an input voltage based on a polarity indicator and a DAC input code, to maintain monotonicity.

Abstract: Dual-string digital-to-analog converters (DACs), and related circuits, systems, and methods are disclosed. In embodiments disclosed herein, a primary voltage divider of the dual string-DAC is comprised of at least one adjusting circuit. The adjusting circuit is configured to maintain the ideal voltage of a selected resistor node pair across a secondary voltage divider circuit in response to a primary switch unit selecting a selected resistor node pair. In this manner, impedance isolation is not required between a primary voltage divider and the secondary voltage divider circuit of the dual-string DAC. As a result, as non-limiting examples, the area on an integrated circuit (IC) for a dual-string DAC may be decreased, power consumption of the DAC may be decreased, and/or the dual-string DAC may have increased performance by not requiring a settling time.

Abstract: A bypass low dropout regulator has a pass gate coupled to a voltage rail. The pass gate receives a pass gate control signal on a pass gate control line and controllably drops a voltage from a rail to a regulated output in accordance with the pass gate control signal. A differential amplifier generates the pass gate control voltage using a reference and feedback from the regulated output. A bypass switch selectively bypasses the regulator control signal, in response to a bypass signal, by placing a pass gate ON voltage on the pass gate control line. Optionally, and ON-OFF mode circuit selectively disables the pass gate in response to a system ON-OFF signal.

Abstract: A switchable bias current biases, in an operational state, a differential amplifier with a full-slew bias current. A system on/off signal transitions from an operational state to a power-down state. The transition disables the differential amplifier and switches the switchable bias current to a reduced slew bias current. The system on/off signal transitions from the power-down state to the operational state, the differential amplifier is enabled, and the switchable bias current is delayed, by a reduced slew duration, from switching to the full-slew bias current. The enabled differential amplifier slews toward a reference voltage at a reduced slew rate caused by the reduced slew bias current. The switchable bias current, after the reduced slew duration, switches to the full-slew bias current. Optionally, a regulated pass gate is disabled in response to the system on/off signal transitioning from the operational state to the power-down state.

Abstract: Methods and apparatus for a successive approximation register analog to digital converter are provided. In an example, provided is a method for digitally representing an analog input signal. A bit of the digital output signal is generated by altering a test voltage by an amount comparable to a weight afforded to the bit, comparing the altered test voltage with the analog input signal to create a comparison output, switching a two-to-one multiplexer to select the comparison output instead of a preceding shift-successive approximation register block output, storing the comparison output in a flip-flop, inhibiting clocking of the flip-flop, and outputting the comparison output from the flip-flop as the bit of the digital output signal.

Abstract: An adaptive low dropout (LDO) regulator includes a load-based bias controller that generates a bias control signal based on the output load current, and has a differential amplifier with a bias adjustment that receives the bias control signal and responds by adjusting a bias of a transistor within the adaptive LOD regulator. Optionally, the bias control signal is generated according to a hysteresis rule. Optionally, the adaptive LOD regulator includes an adaptive load-based compensation network having a zero, the zero having a location based, at least in part, one more of an adjustable resistance or capacitance value controlled by the load-based bias controller.

Abstract: A transient response accelerated (TRA) low dropout (LDO) regulator has an error amplifier having a feedback input, and a reference input configured to receive a reference voltage, and an output that controls a pass gate. The pass gate output voltage is applied to the feedback input. A transient response accelerator (TRA) circuit detects a rapid voltage drop on the pass gate output and, in response, applies a pulse control that rapidly lowers the resistance of the pass gate.