Patents by Inventor Dheemanth Nagaraj

Dheemanth Nagaraj has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7996710
    Abstract: A method is provided for managing defects in a semiconductor memory system having a plurality of addressable locations. In the method, a first plurality of the addressable locations is allocated as in-use locations, and a second plurality of the addressable locations is allocated as spare locations. A plurality of sets of the in-use locations, wherein each of the sets is associated with a memory defect, is determined. At least one of the sets includes a different number of in-use locations than another of the sets. Each of the sets of the in-use locations is associated with at least one corresponding set of the spare locations. Each of a plurality of data requests that is associated with one of the sets of the in-use locations is directed to the at least one corresponding set of the spare locations.
    Type: Grant
    Filed: April 25, 2007
    Date of Patent: August 9, 2011
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Dheemanth Nagaraj, Larry J. Thayer
  • Publication number: 20110078492
    Abstract: Methods and apparatus relating to home agent data and memory management are described. In one embodiment, a scrubber logic corrects an error at a location in a memory corresponding to a target address by writing back the corrected version of data to the target location. In an embodiment, a map out logic maps out an index or way of a directory cache in response to a number of errors, corresponding to the directory cache, exceeding a threshold value. Other embodiments are also disclosed.
    Type: Application
    Filed: September 30, 2009
    Publication date: March 31, 2011
    Inventors: Ganesh Kumar, Dheemanth Nagaraj, Vincent R. Freytag, Eric Delano, Gregory S. Averill
  • Publication number: 20110078384
    Abstract: Methods and apparatus relating to memory mirroring and migration at a Home Agent (HA) are described. In one embodiment, a home agent may mirror its data at a slave agent. In some embodiments, a bit in a directory may indicate status of cache lines. Other embodiments are also disclosed.
    Type: Application
    Filed: September 30, 2009
    Publication date: March 31, 2011
    Inventors: Ganesh Kumar, Dheemanth Nagaraj, Vincent R. Freytag, Eric Delano, Gregory S. Averill
  • Publication number: 20100332767
    Abstract: In one embodiment, a method includes receiving a read request from a first caching agent and if a directory entry associated with the request is in an unknown state, an invalidating snoop message is sent to at least one other caching agent to invalidate information in a cache location of the other caching agent corresponding to the location of the read request, to enable setting of the directory entry into a known state. Other embodiments are described and claimed.
    Type: Application
    Filed: June 26, 2009
    Publication date: December 30, 2010
    Inventors: Ganesh Kumar, Dheemanth Nagaraj, Vincent R. Freytag, Eric Delano, Gregory S. Averill
  • Publication number: 20080270675
    Abstract: A method is provided for managing defects in a semiconductor memory system having a plurality of addressable locations. In the method, a first plurality of the addressable locations is allocated as in-use locations, and a second plurality of the addressable locations is allocated as spare locations. A plurality of sets of the in-use locations, wherein each of the sets is associated with a memory defect, is determined. At least one of the sets includes a different number of in-use locations than another of the sets. Each of the sets of the in-use locations is associated with at least one corresponding set of the spare locations. Each of a plurality of data requests that is associated with one of the sets of the in-use locations is directed to the at least one corresponding set of the spare locations.
    Type: Application
    Filed: April 25, 2007
    Publication date: October 30, 2008
    Inventors: Dheemanth Nagaraj, Larry J. Thayer
  • Publication number: 20080270826
    Abstract: A method comprises detecting a defective area in a Dynamic Random Access Memory (DRAM). The method further comprises establishing a redundant memory buffer at a per-memory module level. The method still further comprises loading the redundant memory buffer with a copy of data from the defective area. The method additionally comprises substituting data from the redundant memory buffer for data stored in the defective area upon a memory access to the defective area.
    Type: Application
    Filed: April 30, 2007
    Publication date: October 30, 2008
    Inventors: Mark SHAW, Larry Thayer, Chris Petersen, Lidia Warnes, Dheemanth Nagaraj