Patents by Inventor Dheepakkumaran Jayaraman

Dheepakkumaran Jayaraman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10473720
    Abstract: In one embodiment, a test system comprises: a plurality of test partitions and a centralized controller configured to coordinate testing between the plurality of test partitions. At least one of the plurality of test partitions comprises: a partition test interface controller configured to control testing within at least one test partition in accordance with dynamic selection of a test mode, and at least one test chain configured to perform test operations. The dynamic selection of the test mode and control of testing within a test partition can be independent of selection of a test mode and control in others of the plurality of test partitions. In one embodiment, a free running clock signal is coupled to a test partition, and the partition test mode controller transforms the free running clock signal into a local partition test clock which is controlled in accordance with the dynamic selection of the test mode.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: November 12, 2019
    Assignee: Nvidia Corporation
    Inventors: Pavan Kumar Datla Jagannadha, Dheepakkumaran Jayaraman, Anubhav Sinha, Karthikeyan Natarajan, Shantanu Sarangi, Amit Sanghani, Milind Sonawane, Mahmut Yilmaz
  • Patent number: 10444280
    Abstract: Granular dynamic test systems and methods facilitate efficient and effective timing of test operations. In one embodiment, a chip test system comprises: a first test partition operable to perform test operations based upon a first local test clock signal; a second test partition operable to perform test operations based upon a second local test clock signal; and a centralized controller configured to coordinate testing between the plurality of test partitions, wherein the coordination includes managing communication of test information between the plurality of test partitions and external pins. In one exemplary implementation, a trigger edge of the first local test clock signal is staggered with respect to a trigger edge of the second local test clock signal, wherein the stagger is coordinated to mitigate power consumption by test operations in the first test partition and test operations in the second test partition.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: October 15, 2019
    Assignee: NVIDIA CORPORATION
    Inventors: Dheepakkumaran Jayaraman, Karthikeyan Natarajan, Shantanu Sarangi, Amit Sanghani, Milind Sonawane, Sailendra Chadalavda, Jonathon E. Colburn, Kevin Wilder, Mahmut Yilmaz, Pavan Kumar Datla Jagannadha
  • Publication number: 20170115352
    Abstract: Granular dynamic test systems and methods facilitate efficient and effective timing of test operations. In one embodiment, a chip test system comprises: a first test partition operable to perform test operations based upon a first local test clock signal; a second test partition operable to perform test operations based upon a second local test clock signal; and a centralized controller configured to coordinate testing between the plurality of test partitions, wherein the coordination includes managing communication of test information between the plurality of test partitions and external pins. In one exemplary implementation, a trigger edge of the first local test clock signal is staggered with respect to a trigger edge of the second local test clock signal, wherein the stagger is coordinated to mitigate power consumption by test operations in the first test partition and test operations in the second test partition.
    Type: Application
    Filed: October 27, 2016
    Publication date: April 27, 2017
    Inventors: Dheepakkumaran Jayaraman, Karthikeyan Natarajan, Shantanu Sarangi, Amit Sanghani, Milind Sonawane, Sailendra Chadalavda, Jonathon E. Colburn, Kevin Wilder, Mahmut Yilmaz
  • Publication number: 20170115351
    Abstract: In one embodiment, a test system comprises: a plurality of test partitions and a centralized controller configured to coordinate testing between the plurality of test partitions. At least one of the plurality of test partitions comprises: a partition test interface controller configured to control testing within at least one test partition in accordance with dynamic selection of a test mode, and at least one test chain configured to perform test operations. The dynamic selection of the test mode and control of testing within a test partition can be independent of selection of a test mode and control in others of the plurality of test partitions. In one embodiment, a free running clock signal is coupled to a test partition, and the partition test mode controller transforms the free running clock signal into a local partition test clock which is controlled in accordance with the dynamic selection of the test mode.
    Type: Application
    Filed: October 27, 2016
    Publication date: April 27, 2017
    Inventors: Pavan Kumar Datla Jagannadha, Dheepakkumaran Jayaraman, Anubhav Sinha, Karthikeyan Natarajan, Shantanu Sarangi, Amit Sanghani, Milind Sonawane, Mahmut Yilmaz