Abstract: A device including a semiconductor die, a first contact, a second contact, a third contact, a first passivation layer, a second passivation layer and an interconnect metal. The semiconductor die may include a plurality of semiconductor layers disposed on a GaAs substrate. The first contact may be electrically coupled to a semiconductor emitter layer. The second contact may be electrically coupled to a semiconductor base layer. The third contact may be electrically coupled to a semiconductor sub-collector layer. The first passivation layer may cover one or more of the semiconductor and the contacts. The first passivation layer may comprise an inorganic insulator. The second passivation layer may comprise an inorganic insulator or organic polymer with low dielectric constant deposited on the passivation layer. The interconnect metal may be coupled to the first contact and separated from the first passivation layer by the second passivation layer.

Abstract: The present disclosure relates to heterojunction bipolar transistors for improved radio frequency (RF) performance. In this regard, a heterojunction bipolar transistor includes a base, an emitter, and a collector. The base is formed over the collector such that a base-collector junction is formed between the base and the collector. The base-collector junction is configured to become forward-biased at a first turn-on voltage. The emitter is formed over the base such that a base-emitter junction is formed between the base and the emitter. The base-emitter junction is configured to become forward-biased at a second turn-on voltage, as opposed to the first turn-on voltage. Notably, the second turn-on voltage is lower than the first turn-on voltage.

Abstract: The present disclosure relates to heterojunction bipolar transistors for improved radio frequency (RF) performance. In this regard, a heterojunction bipolar transistor includes a base, an emitter, and a collector. The base is formed over the collector such that a base-collector junction is formed between the base and the collector. The base-collector junction is configured to become forward-biased at a first turn-on voltage. The emitter is formed over the base such that a base-emitter junction is formed between the base and the emitter. The base-emitter junction is configured to become forward-biased at a second turn-on voltage, as opposed to the first turn-on voltage. Notably, the second turn-on voltage is lower than the first turn-on voltage.

Abstract: A four transistor (4T) memory device is provided. The device includes a first cell transistor and a second cell transistor, the first and second cell transistors coupled to each other and defining latch circuitry having at least one multi-stable node. The device further includes a first access transistor and a second access transistor, the first and second access transistors coupling the at least one multi-stable node to at least one bit-line. In the device, each of the first and second cell transistors and each of the first and second access transistors is a unidirectional field effect transistor configured for conducting current in a first direction and to be insubstantially incapable of conducting current in a second direction.

Abstract: A four transistor (4T) memory device is provided. The device includes a first cell transistor and a second cell transistor, the first and second cell transistors coupled to each other and defining latch circuitry having at least one multi-stable node. The device further includes a first access transistor and a second access transistor, the first and second access transistors coupling the at least one multi-stable node to at least one bit-line. In the device, each of the first and second cell transistors and each of the first and second access transistors is a unidirectional field effect transistor configured for conducting current in a first direction and to be insubstantially incapable of conducting current in a second direction.