Abstract: An active current source load of a fully differential amplifier which is converted into a transconductance (gm) component also at higher frequency by feed-forwarding input signals to their gates. With signal coupling to gate, unity gain bandwidth (UGB) of the amplifier increases by a factor of two. In addition to this, the signal is coupled to source as well to achieve three-fold UGB enhancement. Thus, the effective trans-conductance is gmp at dc and becomes gmp+(gmngate+gmnsrc) at high frequency which triples the UGB when gmp=gmngate/src.

Abstract: An active current source load of a fully differential amplifier which is converted into a transconductance (gm) component also at higher frequency by feed-forwarding input signals to their gates. With signal coupling to gate, unity gain bandwidth (UGB) of the amplifier increases by a factor of two. In addition to this, the signal is coupled to source as well to achieve three-fold UGB enhancement. Thus, the effective trans-conductance is gmp at dc and becomes gmp+(gmngate+gmnsrc) at high frequency which triples the UGB when gmp=gmngate/src.

Abstract: An apparatus is provided which comprises: a first clock line to provide a first clock; a second clock line to provide a second clock; a delay line having a plurality of delay cells, wherein the delay line is coupled to the first and second clock lines, wherein the first clock is to sample the second clock; and circuitry coupled to the delay line, wherein the circuitry is to determine first or latest edge transitions from the outputs of the plurality of delay cells.

Abstract: An apparatus is provided which comprises: a first clock line to provide a first clock; a second clock line to provide a second clock; a delay line having a plurality of delay cells, wherein the delay line is coupled to the first and second clock lines, wherein the first clock is to sample the second clock; and circuitry coupled to the delay line, wherein the circuitry is to determine first or latest edge transitions from the outputs of the plurality of delay cells.

Abstract: An apparatus is provided which comprises: a first clock line to provide a first clock; a second clock line to provide a second clock; a delay line having a plurality of delay cells, wherein the delay line is coupled to the first and second clock lines, wherein the first clock is to sample the second clock; and circuitry coupled to the delay line, wherein the circuitry is to determine first or latest edge transitions from the outputs of the plurality of delay cells.

Abstract: An apparatus is provided which comprises: a first clock line to provide a first clock; a second clock line to provide a second clock; a delay line having a plurality of delay cells, wherein the delay line is coupled to the first and second clock lines, wherein the first clock is to sample the second clock; and circuitry coupled to the delay line, wherein the circuitry is to determine first or latest edge transitions from the outputs of the plurality of delay cells.

Abstract: Some embodiments include apparatuses and methods having a power switching unit to receive a first voltage and provide a second voltage, and a control unit. The control unit can generate control information to control the power switching unit such that a value of the second voltage is less than a value of the first voltage. The control unit can also generate error correction information having a value based on a value of an error in the second voltage. The control unit can operate in a first mode if the error has a value less than a value of a threshold information and in a second mode if the error has a value greater than the value of the threshold information. The control unit can adjust the value of the control information by an amount proportional to the value of the error correction information in the second mode.