Patents by Inventor DHEERAJ SUBBAREDDY

DHEERAJ SUBBAREDDY has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240145395
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.
    Type: Application
    Filed: January 5, 2024
    Publication date: May 2, 2024
    Inventors: MD Altaf HOSSAIN, Ankireddy NALAMALPU, Dheeraj SUBBAREDDY, Robert SANKMAN, Ravindranath V. MAHAJAN, Debendra MALLIK, Ram S. VISWANATH, Sandeep B. SANE, Sriram SRINIVASAN, Rajat AGARWAL, Aravind DASU, Scott WEBER, Ravi GUTALA
  • Publication number: 20230107106
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.
    Type: Application
    Filed: December 12, 2022
    Publication date: April 6, 2023
    Inventors: MD Altaf HOSSAIN, Ankireddy NALAMALPU, Dheeraj SUBBAREDDY, Robert SANKMAN, Ravindranath V. MAHAJAN, Debendra MALLIK, Ram S. VISWANATH, Sandeep B. SANE, Sriram SRINIVASAN, Rajat AGARWAL, Aravind DASU, Scott WEBER, Ravi GUTALA
  • Publication number: 20220114125
    Abstract: A processor having a system on a chip (SOC) architecture comprises one or more central processing units (CPUs) comprising multiple cores. An optical Compute Express Link (CXL) communication path incorporating a logical optical CXL protocol stack path transmits and receives an optical bit stream directly after the link layer, bypassing multiple levels of the CXL protocol stack. A CXL interface controller is connected to the one or more CPUs to enable communication between the CPUs and one or more CXL devices over the optical CXL communication path.
    Type: Application
    Filed: October 9, 2020
    Publication date: April 14, 2022
    Inventors: Anshuman THAKUR, Dheeraj SUBBAREDDY, MD Altaf HOSSAIN, Ankireddy NALAMALPU, Mahesh KUMASHIKAR
  • Publication number: 20220100692
    Abstract: Embodiments herein relate to systems, apparatuses, or processes for improving off-package edge bandwidth by overlapping electrical and optical serialization/deserialization (SERDES) interfaces on an edge of the package. In other implementations, off-package bandwidth for a particular edge of a package may use both an optical fanout and an electrical fanout on the same edge of the package. In embodiments, the optical fanout may use a top surface or side edge of a die and the electrical fanout may use the bottom side edge of the die. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 25, 2020
    Publication date: March 31, 2022
    Inventors: Dheeraj SUBBAREDDY, Ankireddy NALAMALPU, Anshuman THAKUR, MD Altaf HOSSAIN, Mahesh KUMASHIKAR, Kemal AYGÜN, Casey THIELEN, Daniel KLOWDEN, Sandeep B. SANE
  • Publication number: 20220092016
    Abstract: Embodiments herein relate to systems, apparatuses, or techniques for using an optical physical layer die within a system-on-a-chip to optically couple with an optical physical layer die on another package to provide high-bandwidth memory access between the system-on-a-chip and the other package. In embodiments, the other package may be a large optically connected memory device that includes a memory controller coupled with an optical physical layer die, where the memory controller is coupled with memory. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 24, 2020
    Publication date: March 24, 2022
    Inventors: Mahesh K. KUMASHIKAR, Dheeraj SUBBAREDDY, Anshuman THAKUR, MD Altaf HOSSAIN, Ankireddy NALAMALPU, Casey G. THIELEN, Daniel S. KLOWDEN, Kevin P. MA, Sergey Yuryevich SHUMARAYEV, Sandeep SANE, Conor O'KEEFFE
  • Publication number: 20220094434
    Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to characterizing data being transferred from one device to another via an optical link based upon the wavelengths within the optical link on which the data is being carried. In embodiments, the characteristics of this data may include quality of service for the data to be implemented by a field programmable gate array within a heterogeneous storage pool coupled with storage devices, where the quality of service includes minimum threshold values for bandwidth and latency. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 24, 2020
    Publication date: March 24, 2022
    Inventors: Dheeraj SUBBAREDDY, Anshuman THAKUR, Ankireddy NALAMALPU, MD Altaf HOSSAIN
  • Publication number: 20200211969
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.
    Type: Application
    Filed: December 28, 2018
    Publication date: July 2, 2020
    Inventors: MD Altaf HOSSAIN, Ankireddy NALAMALPU, Dheeraj SUBBAREDDY, Robert SANKMAN, Ravindranath V. MAHAJAN, Debendra MALLIK, Ram S. VISWANATH, Sandeep B. SANE, Sriram SRINIVASAN, Rajat AGARWAL, Aravind DASU, Scott WEBER, Ravi GUTALA
  • Publication number: 20200176372
    Abstract: Embodiments of the invention include a stacked die system and methods for forming such systems. In an embodiment, the stacked die system may include a first die. The first die may include a device layer and a plurality of routing layers formed over the device layer. The plurality of routing layers may be segmented into a plurality of sub regions. In an embodiment no conductive traces in the plurality of routing layers pass over a boundary between any of the plurality of sub regions. In an embodiment, the stacked die system may also include a plurality of second dies stacked over the first die. According to an embodiment, at least a two of the second dies are communicatively coupled to each other by a die to die interconnect formed entirely within a single sub region in the first die.
    Type: Application
    Filed: April 1, 2017
    Publication date: June 4, 2020
    Inventors: MD Altaf HOSSAIN, Dinesh SOMASEKHAR, Dheeraj SUBBAREDDY
  • Publication number: 20200144186
    Abstract: A package substrate and a package assembly including a package substrate including a substrate body including a plurality of first contact points on a surface thereof configured for electrical connection to a first die and a plurality of second contact points on the surface configured for electrical connection to a second die; and a bridge coupled to the substrate body, the bridge including active device circuitry that is coupled to ones of the plurality of first contact points and ones of the plurality of second contact points. A method of forming a package assembly including coupling a first die to a package substrate, the package substrate including a bridge substrate including active device circuitry; and coupling a second die to the package substrate, wherein coupling the first die and the second die to the package substrate includes coupling the first die and the second die to the active circuitry.
    Type: Application
    Filed: September 13, 2017
    Publication date: May 7, 2020
    Inventors: Thomas P. THOMAS, Wilfred GOMES, Ravindranath V. MAHAJAN, Rajesh KUMAR, Mark T. BOHR, Dheeraj SUBBAREDDY, Ankireddy NALAMALPU, Mahesh KUMASHIKAR
  • Publication number: 20160283747
    Abstract: Technologies for hardening encryption operations are disclosed. In some embodiments, the technologies harden encryption operations typically performed by kernel mode programs with a secure enclave that may run in user mode and/or in a pre-boot context. In some embodiments, the technologies leverage a shared buffer and a proxy to enable the use of a secure enclave hosted in user mode to perform encryption operations. In additional embodiments, the technologies utilize one or more pre-boot applications to enable the use of a secure enclave in a pre-boot phase, e.g., so as to enable the use of a secure enclave to decrypt data that may be needed to boot a computing device.
    Type: Application
    Filed: March 25, 2015
    Publication date: September 29, 2016
    Applicant: Intel Corporation
    Inventors: BIN CEDRIC XING, RESHMA LAL, DHEERAJ SUBBAREDDY