Abstract: Error-correcting circuit includes: component generating a first output from first and second inputs; error detector generating an error flag indicative of whether or not an error is detected in the first output, based on the first output, and the first and second inputs; correction generator generating a correcting output after a first time period beginning with a timing event, based on the first output, and the first and second inputs; and output generator generating an output after a second time period beginning with the timing event. If the error flag indicates a detected error then the second time period may be longer than the first time period, otherwise it may be not longer, and the error-correcting circuit output may include a combination of the first output and the correcting output whereby the detected error is corrected, otherwise the error-correcting circuit output may correspond directly to the first output.

Abstract: An error-correcting circuit comprises: a component arranged to generate a first output from a first input and a second input; an error detector arranged to generate an error flag indicative of whether or not it has detected an error in the first output, based on the first output, the first input and the second input; a correction generator suitable for generating a correcting output after a first time period beginning with a timing event, based on the first output, the first input and the second input; and an output generator arranged to generate an output of the error-correcting circuit after a second time period beginning with the timing event. If the error flag indicates that an error has been detected in the first output then the second time period may be longer than the first time period, otherwise the second time period may be not longer than the first time period.

Abstract: The disclosed system uses a binary tree which is embedded in a De Bruijn graph to sort the survivor paths based on their path metrics. The system includes a sorting algorithm which is implemented in a pipelined fashion. The same communication structure underlining the De Bruijn graph is used, so that no additional communication overhead is required for sorting. The system implementation is parallel resulting in a high throughput.

Abstract: The RAM is partitioned into modules, each of which appear as the leaf node of a binary interconnect network. This network carries the address/data/control bus which permits the nodes to communicate between themselves and with the outside world. The address, data and control signals are applied to the root node. The most significant address bit is decoded, generating either a left subtree or a right subtree select. The other signals would be buffered and propogated down the tree. The solution process occurs at each level within the bus until finally a single leaf node would be selected. Within the node, then, the internal timing and control unit would access the data requested, sending it up the tree or writing the value on the data bus, into the addressed location.