Patents by Inventor Dhishan Kande
Dhishan Kande has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11848268Abstract: A device including a thin film resistor (TFR) structure. The TFR structure is accessible by one or more conductive vias that extend vertically from an upper metal layer to completely penetrate a TFR layer positioned thereunder. The conductive vias are coupled to one or more sidewalls of the TFR layer at or near the sites of penetration. The TFR structure can be manufactured by a method that includes etching a via trench completely through the TFR layer and a dielectric layer above the TFR layer, and filling the via trench with a conductor coupled to a sidewall of the TFR layer.Type: GrantFiled: July 16, 2021Date of Patent: December 19, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Dhishan Kande, Qi-Zhong Hong, Abbas Ali, Gregory B. Shinn
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Publication number: 20230366581Abstract: An HVAC system includes one or more air quality sensors, each configured to measure an air quality and a thermostat communicatively coupled to the one or more air quality sensors. The thermostat receives indoor air quality measurements from the one or more air quality sensors. An indoor air quality score is determined based at least in part on the received indoor air quality measurements. The thermostat determines, based at least in part on the indoor air quality score, a mitigation action, wherein the mitigation action comprises one or more actions selected from the group of: (i) a filtering action comprising filtering air provided to the space using an air purification subsystem, and (ii) a ventilation action comprising ventilating the space using a ventilation subsystem. The mitigation action is executed, or implemented, by adjusting one or more components of the HVAC system.Type: ApplicationFiled: May 11, 2022Publication date: November 16, 2023Inventors: Sanjeev Hingorani, Henry Greist, Elena Smirnova, Pete Hrejsa, Emile Abi-Habib, Dhishan Kande
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Publication number: 20210343642Abstract: A device including a thin film resistor (TFR) structure. The TFR structure is accessible by one or more conductive vias that extend vertically from an upper metal layer to completely penetrate a TFR layer positioned thereunder. The conductive vias are coupled to one or more sidewalls of the TFR layer at or near the sites of penetration. The TFR structure can be manufactured by a method that includes etching a via trench completely through the TFR layer and a dielectric layer above the TFR layer, and filling the via trench with a conductor coupled to a sidewall of the TFR layer.Type: ApplicationFiled: July 16, 2021Publication date: November 4, 2021Inventors: Dhishan Kande, Qi-Zhong Hong, Abbas Ali, Gregory B. Shinn
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Patent number: 11101212Abstract: A device including a thin film resistor (TFR) structure. The TFR structure is accessible by one or more conductive vias that extend vertically from an upper metal layer to completely penetrate a TFR layer positioned thereunder. The conductive vias are coupled to one or more sidewalls of the TFR layer at or near the sites of penetration. The TFR structure can be manufactured by a method that includes etching a via trench completely through the TFR layer and a dielectric layer above the TFR layer, and filling the via trench with a conductor coupled to a sidewall of the TFR layer.Type: GrantFiled: May 28, 2019Date of Patent: August 24, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Dhishan Kande, Qi-Zhong Hong, Abbas Ali, Gregory B. Shinn
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Patent number: 10840322Abstract: An integrated circuit (IC) includes a substrate with a semiconductor surface layer including functional circuitry having a plurality of interconnected transistors including a dielectric layer thereon with a metal stack including a plurality of metal levels over the dielectric layer. A thin film resistor (TFR) layer including at least one metal is within the metal stack. At least one capacitor is within the metal stack including a capacitor dielectric layer over a metal bottom plate formed from one of the metal levels. The capacitor top plate is formed from the TFR layer on the capacitor dielectric layer and there is at least one resistor lateral to the capacitor formed from the same TFR layer.Type: GrantFiled: March 29, 2018Date of Patent: November 17, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Dhishan Kande, Ye Shao, David Curran
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Patent number: 10741473Abstract: An integrated circuit has a substrate including semiconductor material and a resistor in an interconnect region, above a first level of interconnect lines. The integrated circuit further includes an electrically isolated thermal conduit having one or more interconnect lines in every interconnect level lower than the resistor. The interconnect lines of the thermal conduit are directly connected through one or more vertical interconnects, including contacts, and possibly vias, to a gate structure located on a dielectric material over the semiconductor material of the substrate. The thermal conduit is electrically isolated from the resistor, from all active components in the integrated circuit, and from the semiconductor material of the substrate.Type: GrantFiled: October 16, 2019Date of Patent: August 11, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Dhishan Kande, Archana Venugopal
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Publication number: 20200212167Abstract: A method of fabricating an integrated circuit (IC) includes providing a substrate having a semiconductor surface layer comprising an unpatterned resistive layer. Measurements are obtained of a characteristic of the unpatterned resistive layer at each of a plurality of locations over the substrate. The unpatterned resistive layer is modified, such as by targeted removal of layer material, in response to the measurements such that the measured characteristic is more uniform across the substrate. A resistor on the IC is defined from the unpatterned resistive layer after the modifying.Type: ApplicationFiled: December 26, 2018Publication date: July 2, 2020Inventors: BHASKAR SRINIVASAN, BRIAN GOODLIN, DHISHAN KANDE
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Patent number: 10680056Abstract: A method of fabricating an integrated circuit (IC) includes providing a substrate having a semiconductor surface layer comprising an unpatterned resistive layer. Measurements are obtained of a characteristic of the unpatterned resistive layer at each of a plurality of locations over the substrate. The unpatterned resistive layer is modified, such as by targeted removal of layer material, in response to the measurements such that the measured characteristic is more uniform across the substrate. A resistor on the IC is defined from the unpatterned resistive layer after the modifying.Type: GrantFiled: December 26, 2018Date of Patent: June 9, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Bhaskar Srinivasan, Brian Goodlin, Dhishan Kande
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Publication number: 20200051893Abstract: An integrated circuit has a substrate including semiconductor material and a resistor in an interconnect region, above a first level of interconnect lines. The integrated circuit further includes an electrically isolated thermal conduit having one or more interconnect lines in every interconnect level lower than the resistor. The interconnect lines of the thermal conduit are directly connected through one or more vertical interconnects, including contacts, and possibly vias, to a gate structure located on a dielectric material over the semiconductor material of the substrate. The thermal conduit is electrically isolated from the resistor, from all active components in the integrated circuit, and from the semiconductor material of the substrate.Type: ApplicationFiled: October 16, 2019Publication date: February 13, 2020Inventors: Dhishan Kande, Archana Venugopal
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Patent number: 10475725Abstract: An integrated circuit has a substrate including semiconductor material and a resistor in an interconnect region, above a first level of interconnect lines. The integrated circuit further includes an electrically isolated thermal conduit having one or more interconnect lines in every interconnect level lower than the resistor. The interconnect lines of the thermal conduit are directly connected through one or more vertical interconnects, including contacts, and possibly vias, to a gate structure located on a dielectric material over the semiconductor material of the substrate. The thermal conduit is electrically isolated from the resistor, from all active components in the integrated circuit, and from the semiconductor material of the substrate.Type: GrantFiled: November 8, 2017Date of Patent: November 12, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Dhishan Kande, Archana Venugopal
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Patent number: 10439020Abstract: A method of fabricating integrated circuits (ICs) includes depositing a dielectric liner layer on a substrate including a semiconductor surface having a plurality of IC die formed therein each including functional circuitry including a plurality of interconnected transistors. A thin film resistor (TFR) layer including chromium (Cr) is deposited on the dielectric liner layer. The substrate is loaded into a hardmask layer deposition tool that includes a plasma source. The TFR layer is in-situ plasma pre-treated including flowing at least one inert gas and at least one oxidizing gas while in the hardmask layer deposition tool. A hardmask layer is deposited after the plasma pre-treating while remaining in the hardmask layer deposition tool. A pattern is formed on the hardmask layer, and the hardmask layer and TFR layer are etched stopping in the dielectric liner layer to form at least one resistor from the defined TFR layer.Type: GrantFiled: December 27, 2017Date of Patent: October 8, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Abbas Ali, Dhishan Kande, Qi-Zhong Hong, Shih Chang Chang
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Publication number: 20190305074Abstract: An integrated circuit (IC) includes a substrate with a semiconductor surface layer including functional circuitry having a plurality of interconnected transistors including a dielectric layer thereon with a metal stack including a plurality of metal levels over the dielectric layer. A thin film resistor (TFR) layer including at least one metal is within the metal stack. At least one capacitor is within the metal stack including a capacitor dielectric layer over a metal bottom plate formed from one of the metal levels. The capacitor top plate is formed from the TFR layer on the capacitor dielectric layer and there is at least one resistor lateral to the capacitor formed from the same TFR layer.Type: ApplicationFiled: March 29, 2018Publication date: October 3, 2019Inventors: Dhishan Kande, Ye Shao, David Curran
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Publication number: 20190295948Abstract: A device including a thin film resistor (TFR) structure. The TFR structure is accessible by one or more conductive vias that extend vertically from an upper metal layer to completely penetrate a TFR layer positioned thereunder. The conductive vias are coupled to one or more sidewalls of the TFR layer at or near the sites of penetration. The TFR structure can be manufactured by a method that includes etching a via trench completely through the TFR layer and a dielectric layer above the TFR layer, and filling the via trench with a conductor coupled to a sidewall of the TFR layer.Type: ApplicationFiled: May 28, 2019Publication date: September 26, 2019Inventors: Dhishan Kande, Qi-Zhong Hong, Abbas Ali, Gregory B. Shinn
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Patent number: 10361095Abstract: A method of fabricating an integrated circuit (IC) includes depositing an aluminum-containing metal interconnect layer at a first temperature over a semiconductor device having a plurality of transistors. The metal interconnect layer is annealed at a maximum annealing temperature that is less than the first temperature. The metal interconnect layer is patterned after the annealing, thereby interconnecting the transistors.Type: GrantFiled: May 16, 2018Date of Patent: July 23, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Abbas Ali, Dhishan Kande, Qi-Zhong Hong, Young-Joon Park, Kyle McPherson
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Publication number: 20190221516Abstract: A device including a thin film resistor (TFR) structure. The TFR structure is accessible by one or more conductive vias that extend vertically from an upper metal layer to completely penetrate a TFR layer positioned thereunder. The conductive vias are coupled to one or more sidewalls of the TFR layer at or near the sites of penetration. The TFR structure can be manufactured by a method that includes etching a via trench completely through the TFR layer and a dielectric layer above the TFR layer, and filling the via trench with a conductor coupled to a sidewall of the TFR layer.Type: ApplicationFiled: January 16, 2018Publication date: July 18, 2019Inventors: Dhishan Kande, Qi-Zhong Hong, Abbas Ali, Gregory B. Shinn
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Patent number: 10354951Abstract: A device including a thin film resistor (TFR) structure. The TFR structure is accessible by one or more conductive vias that extend vertically from an upper metal layer to completely penetrate a TFR layer positioned thereunder. The conductive vias are coupled to one or more sidewalls of the TFR layer at or near the sites of penetration. The TFR structure can be manufactured by a method that includes etching a via trench completely through the TFR layer and a dielectric layer above the TFR layer, and filling the via trench with a conductor coupled to a sidewall of the TFR layer.Type: GrantFiled: January 16, 2018Date of Patent: July 16, 2019Assignee: Texas Instruments IncorporatedInventors: Dhishan Kande, Qi-Zhong Hong, Abbas Ali, Gregory B. Shinn
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Publication number: 20190198603Abstract: A method of fabricating integrated circuits (ICs) includes depositing a dielectric liner layer on a substrate including a semiconductor surface having a plurality of IC die formed therein each including functional circuitry including a plurality of interconnected transistors. A thin film resistor (TFR) layer including chromium (Cr) is deposited on the dielectric liner layer. The substrate is loaded into a hardmask layer deposition tool that includes a plasma source. The TFR layer is in-situ plasma pre-treated including flowing at least one inert gas and at least one oxidizing gas while in the hardmask layer deposition tool. A hardmask layer is deposited after the plasma pre-treating while remaining in the hardmask layer deposition tool. A pattern is formed on the hardmask layer, and the hardmask layer and TFR layer are etched stopping in the dielectric liner layer to form at least one resistor from the defined TFR layer.Type: ApplicationFiled: December 27, 2017Publication date: June 27, 2019Inventors: ABBAS ALI, DHISHAN KANDE, QI-ZHONG HONG, SHIH CHANG CHANG
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Publication number: 20190139861Abstract: An integrated circuit has a substrate including semiconductor material and a resistor in an interconnect region, above a first level of interconnect lines. The integrated circuit further includes an electrically isolated thermal conduit having one or more interconnect lines in every interconnect level lower than the resistor. The interconnect lines of the thermal conduit are directly connected through one or more vertical interconnects, including contacts, and possibly vias, to a gate structure located on a dielectric material over the semiconductor material of the substrate. The thermal conduit is electrically isolated from the resistor, from all active components in the integrated circuit, and from the semiconductor material of the substrate.Type: ApplicationFiled: November 8, 2017Publication date: May 9, 2019Applicant: Texas Instruments IncorporatedInventors: Dhishan Kande, Archana Venugopal
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Publication number: 20190074193Abstract: A method of fabricating an integrated circuit (IC) includes depositing an aluminum-containing metal interconnect layer at a first temperature over a semiconductor device having a plurality of transistors. The metal interconnect layer is annealed at a maximum annealing temperature that is less than the first temperature. The metal interconnect layer is patterned after the annealing, thereby interconnecting the transistors.Type: ApplicationFiled: May 16, 2018Publication date: March 7, 2019Inventors: Abbas ALI, Dhishan KANDE, Qi-Zhong HONG, Young-Joon PARK, Kyle MCPHERSON
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Patent number: 10211278Abstract: A device and method for fabricating an integrated circuit (IC) chip is disclosed. The method includes depositing a first thin film resistor material on a first inter-level dielectric (ILD) layer; depositing an etch retardant layer overlying the first thin film resistor material; and patterning and etching the etch retardant layer and the first thin film resistor material to form a first resistor. The method continues with depositing a second ILD layer overlying the first resistor; and patterning and etching the second ILD layer using a first etch chemistry to form vias through the second ILD layer and the etch retardant layer to the first resistor. The etch retardant layer is selective to a first etch chemistry and the thickness of the etch retardant layer is such that the via etching process removes substantially all exposed portions of the etch retardant layer and substantially prevents consumption of the underlying first thin film resistor material.Type: GrantFiled: July 11, 2017Date of Patent: February 19, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Abbas Ali, Dhishan Kande, Qi-Zhong Hong