Patents by Inventor Dhori Kedar Janardan
Dhori Kedar Janardan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230403838Abstract: A memory cell including a set of active regions that overlay a set of gate regions to form a pair of cross-coupled inverters. A first active region extends along a first axis. A first gate region extends transversely to the first active region and overlays the first active region to form a first transistor of the pair of cross-coupled inverters. A second gate region extends transversely to the first active region and overlays the first active region to form a second transistor of the pair of cross-coupled inverters. A second active region extends along a second axis and overlays the first gate region to form a third transistor of the pair of cross-coupled inverters. A fourth active region extending along a third axis and overlays a gate region to form a transistor of a read port.Type: ApplicationFiled: August 23, 2023Publication date: December 14, 2023Applicant: STMicroelectronics International N.V.Inventors: Shafquat Jahan AHMED, Dhori Kedar JANARDAN
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Patent number: 10311944Abstract: A first transistor has a first conduction terminal coupled to a second bit line, a second conduction terminal coupled to a bit line node, and a control terminal biased by a second control signal. A second transistor has a first conduction terminal coupled to a second complementary bit line, a second conduction terminal coupled to a complementary bit line node, and a control terminal biased by the second control signal. A first replica transistor has a first conduction terminal coupled to the second bit line, a second conduction terminal coupled to the complementary bit line node, and a control terminal biased such that the first replica transistor is off. A second replica transistor has a first conduction terminal coupled to the second complementary bit line, a second conduction terminal coupled to the bit line node, and a control terminal biased such that the second replica transistor is off.Type: GrantFiled: July 2, 2018Date of Patent: June 4, 2019Assignee: STMicroelectronics International N.V.Inventors: Dhori Kedar Janardan, Abhishek Pathak, Shishir Kumar
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Publication number: 20190035454Abstract: A first transistor has a first conduction terminal coupled to a second bit line, a second conduction terminal coupled to a bit line node, and a control terminal biased by a second control signal. A second transistor has a first conduction terminal coupled to a second complementary bit line, a second conduction terminal coupled to a complementary bit line node, and a control terminal biased by the second control signal. A first replica transistor has a first conduction terminal coupled to the second bit line, a second conduction terminal coupled to the complementary bit line node, and a control terminal biased such that the first replica transistor is off. A second replica transistor has a first conduction terminal coupled to the second complementary bit line, a second conduction terminal coupled to the bit line node, and a control terminal biased such that the second replica transistor is off.Type: ApplicationFiled: July 2, 2018Publication date: January 31, 2019Applicant: STMicroelectronics International N.V.Inventors: Dhori Kedar Janardan, Abhishek Pathak, Shishir Kumar
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Patent number: 10037794Abstract: A first transistor has a first conduction terminal coupled to a second bit line, a second conduction terminal coupled to a bit line node, and a control terminal biased by a second control signal. A second transistor has a first conduction terminal coupled to a second complementary bit line, a second conduction terminal coupled to a complementary bit line node, and a control terminal biased by the second control signal. A first replica transistor has a first conduction terminal coupled to the second bit line, a second conduction terminal coupled to the complementary bit line node, and a control terminal biased such that the first replica transistor is off. A second replica transistor has a first conduction terminal coupled to the second complementary bit line, a second conduction terminal coupled to the bit line node, and a control terminal biased such that the second replica transistor is off.Type: GrantFiled: July 26, 2017Date of Patent: July 31, 2018Assignee: STMicroelectronics International N.V.Inventors: Dhori Kedar Janardan, Abhishek Pathak, Shishir Kumar
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Publication number: 20170316820Abstract: Read stability of a memory is enhanced in low voltage operation mode by selectively boosting a cell supply voltage for a row of memory cells. The boosted voltage results from a capacitive coupling to the word line in that row. The capacitive coupling is implemented by running the metal line of the power supply line for the cell supply voltage and the metal line for the word line adjacent to each other in a common metallization level. The selective voltage boost is controlled in response to operation of a modified memory cell exhibiting a deteriorated write margin. An output of the modified memory cell is compared to a threshold to generate a signal for controlling the selective voltage boost. Word line under-voltage circuitry is further provided to control application of an under-voltage to the word line.Type: ApplicationFiled: March 2, 2017Publication date: November 2, 2017Applicant: STMicroelectronics International N.V.Inventors: Ashish Kumar, Vinay Kumar, Dhori Kedar Janardan
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Patent number: 8441874Abstract: A memory circuit includes a memory cell configured to be re-writable. A write enable circuit is configured to enable writing a signal via a pair of bit lines to the memory cell depending on a write signal. A charge supply circuit is configured to supply a charge to at least one of the pair of bit lines. A charge supply controller is configured to control the charge supply circuit to disable the supply of charge and couple the write enable circuit to at least one of the pair of bit lines after a first determined period following the reception of the write signal.Type: GrantFiled: December 28, 2010Date of Patent: May 14, 2013Assignee: STMicroelectronics International N.V.Inventors: Rakesh Kumar Sinha, Dhori Kedar Janardan, Sachin Gulyani
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Patent number: 8411518Abstract: A memory circuit includes a memory cell configured to be re-writable. A write enable circuit is configured to enable writing a signal via a pair of bit lines to the memory cell depending on a write signal. A charge supply circuit is configured to supply a charge to at least one of the pair of bit lines. A charge supply controller is configured to control the charge supply circuit to supply the charge dependent on at least one of the temperature of the memory circuit and the potential difference supply of the memory circuit.Type: GrantFiled: December 29, 2010Date of Patent: April 2, 2013Assignee: STMicroelectronics Pvt. Ltd.Inventors: Dhori Kedar Janardan, Rakesh Kumar Sinha, Sachin Gulyani
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Publication number: 20120170391Abstract: A memory circuit includes a memory cell configured to be re-writable. A write enable circuit is configured to enable writing a signal via a pair of bit lines to the memory cell depending on a write signal. A charge supply circuit is configured to supply a charge to at least one of the pair of bit lines. A charge supply controller is configured to control the charge supply circuit to supply the charge dependent on at least one of the temperature of the memory circuit and the potential difference supply of the memory circuit.Type: ApplicationFiled: December 29, 2010Publication date: July 5, 2012Applicant: STMicroelectronics Pvt. Ltd.Inventors: Dhori Kedar Janardan, Rakesh Kumar Sinha, Sachin Gulyani
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Publication number: 20120163110Abstract: A memory circuit includes a memory cell configured to be re-writable. A write enable circuit is configured to enable writing a signal via a pair of bit lines to the memory cell depending on a write signal. A charge supply circuit is configured to supply a charge to at least one of the pair of bit lines. A charge supply controller is configured to control the charge supply circuit to disable the supply of charge and couple the write enable circuit to at least one of the pair of bit lines after a first determined period following the reception of the write signal.Type: ApplicationFiled: December 28, 2010Publication date: June 28, 2012Applicant: STMicroelectronics Pvt. Ltd.Inventors: Rakesh Kumar Sinha, Dhori Kedar Janardan, Sachin Gulyani