Abstract: In an example, a memory control device includes an output circuit, an output delay unit, and a write-levelization controller. The output circuit is coupled to provide an output signal comprising a data signal or data strobe signal for a synchronous dynamic random access memory (SDRAM) system having a plurality of ranks. The output delay unit is coupled to apply an output delay to a bitstream to be transmitted to generate the output signal. The output delay includes an aggregate of a de-skew delay and a write-levelization delay. The write-levelization delay controller is coupled to adjust the write-levelization delay for each write transaction to the SDRAM system of a plurality of write transactions based on a selected rank of the plurality of ranks. The de-skew delay is the same across the plurality of ranks for each of the plurality of write transactions.

Abstract: In an example, a memory control device includes an output circuit, an output delay unit, and a write-levelization controller. The output circuit is coupled to provide an output signal comprising a data signal or data strobe signal for a synchronous dynamic random access memory (SDRAM) system having a plurality of ranks. The output delay unit is coupled to apply an output delay to a bitstream to be transmitted to generate the output signal. The output delay includes an aggregate of a de-skew delay and a write-levelization delay. The write-levelization delay controller is coupled to adjust the write-levelization delay for each write transaction to the SDRAM system of a plurality of write transactions based on a selected rank of the plurality of ranks. The de-skew delay is the same across the plurality of ranks for each of the plurality of write transactions.

Abstract: A method, non-transitory computer readable medium and apparatus for synchronizing a clock signal data path, a write strobe signal data path and a write data signal data path are disclosed. The method determines an amount of phase shift between the clock signal data path and the write strobe signal data path and between the clock signal data path and the write data signal data path, gates a clock signal to generate strobe clock signals that are phase shifted by at least one phase shift, applies a fine phase shift to the strobe clock signals where the strobe clock signals have an overall phase shift that is approximately equal to the amount of phase shift, and synchronizes a launch of the clock signal data path, the write strobe signal data path, and the write data signal data path using the strobe clock signals with the overall phase shift.

Abstract: Enabling security of a computer system. Physical proximity of an authorized user with the computer system is detected without requiring the authorized user to physically access the interior of the computer system is monitored. In response to detecting the physical proximity of an authorized user, the authorized user is allowed access to privileged operations of the computer system.

Abstract: Firmware and/or a chipset of a computer system in an example makes a determination of a state of the computer system and sets the chipset in one of a plurality of modes based on the determination of the state of the computer system.

Abstract: Various embodiments of a method of configuring a predefined set of electrically isolated blades to function as a single blade are described. In one embodiment, a configuration rule is accessed, wherein a portion of the configuration rule assigns roles to management processors coupled with the predefined set of conjoined blades of a blade partition. Assistant management processors are directed to configure blade manageability modules to support the assigned roles. The blade manageability modules are coupled with the management processors. In one embodiment, the assistant management processors are directed to configure resources to be shared across the blade partition according to the configuration rule. After determining that the conjoined blades are configured according to the configuration rule, the conjoined blades are initialized. Thus, the conjoined blades are coordinated to function as a single blade.

Abstract: A firmware selector is provided for a computer that includes a processor. The selector receives the identity of the processor, and in response to the identity, causes the processor to access firmware that corresponds to the processor. Because such a selector can automatically direct the processor to the appropriate firmware when the computer stores multiple firmware, the selector allows a customer to change the processor without requiring him to change the firmware memory or the board on which the firmware memory resides.

Abstract: A firmware selector is provided for a computer that includes a processor. The selector receives the identity of the processor, and in response to the identity, causes the processor to access firmware that corresponds to the processor. Because such a selector can automatically direct the processor to the appropriate firmware when the computer stores multiple firmware, the selector allows a customer to change the processor without requiring him to change the firmware memory or the board on which the firmware memory resides.

Abstract: A data-protection circuit selectively allows access to data stored in a memory. Specifically, the circuit receives an authorization key and allows access to the data if the authorization key equals a predetermined value. Such a circuit can be used to prevent an unauthorized agent such as an unauthorized update package, a virus, or a hacker from reading or corrupting data such as firmware because the agent presumably will not have or be able to obtain the authorization key. Furthermore, by disposing the data-protection circuit and memory on separate integrated circuits (ICs), one can implement data protection without altering the design of the memory IC. This allows one to implement data protection for off-the-shelf memory ICs that include no integrated protection circuit. For example, one can implement the data-protection circuit in a field-programmable gate array (FPGA) that is coupled to but separate from the memory IC.