Abstract: A method of determining fraud includes: receiving a transaction request associated with a first payment transaction between a merchant and a user from a merchant system; generating a first risk score based on the transaction request and a first set pot of transaction data received prior to the transaction request; processing a transaction request approval based on the first risk score not satisfying a first threshold; receiving a risk score request associated with the first payment transaction, where the risk score request is received after the transaction request has been approved; generating a second risk score based on a second set of transaction data received after the first risk score is determined; and automatically classifying the first payment transaction as potentially fraudulent in response to determining that the second risk score satisfies a second threshold.

Abstract: A system, a method, and a machine-readable medium for overclocking a computer system is provided. An example of a method for overclocking a computer system includes predicting a stable operating frequency for a central processing unit (CPU) in a target system based, at least in part, on a model generated from data collected for a test system. An operating frequency for the CPU is adjusted to the stable operating frequency. A benchmark test is run to confirm that the CPU is operating within limits.

Abstract: A method of automatic overclocking of a silicon part or chip, such as a central processing unit (CPU) is disclosed. A range of clock frequencies of both the CPU and a cache of a computer system are tested, with parameters being monitored, safety limits of the computer system being ensured, and benchmark tests being run, before arriving at a CPU and cache frequencies based on a selected benchmark score.

Abstract: A system, a method, and a machine-readable medium for overclocking a computer system is provided. An example of a method for overclocking a computer system includes predicting a stable operating frequency for a central processing unit (CPU) in a target system based, at least in part, on a model generated from data collected for a test system. An operating frequency for the CPU is adjusted to the stable operating frequency. A benchmark test is run to confirm that the CPU is operating within limits.

Abstract: An example non-transitory computer-readable storage medium comprises instructions that, when executed by a processing resource of a computing device, cause the processing resource to determine a portion of an interface moved from a first display to a second display. The instructions further cause the processing resource to compare the portion of the interface moved from the first display to the second display to a threshold. The instructions further cause the processing resource to move the interface automatically from the first display to the second display responsive to a determination that the portion of the interface moved to the second display exceeds the threshold.

Abstract: An example non-transitory computer-readable storage medium comprises instructions that, when executed by a processing resource of a computing device, cause the processing resource to present an interface of an application on a first display of the computing device. The instructions further cause the processing resource to, in response to receiving a selection of a boundary that defines a portion of the interface, present the portion on a second display of the computing device.

Abstract: A method of automatic overclocking of a silicon part or chip, such as a central processing unit (CPU) is disclosed. A range of clock frequencies of both the CPU and a cache of a computer system are tested, with parameters being monitored, safety limits of the computer system being ensured, and benchmark tests being run, before arriving at a CPU and cache frequencies based on a selected benchmark score.

Abstract: An output buffer with a switchable output impedance designed for driving a terminated signal line. The buffer includes a drive circuit, and a means for switching the output impedance of the drive circuit between a first, relatively low output impedance when the output buffer is operated in a ‘normal’ mode, and a second output impedance which is greater than the first output impedance when operated in a ‘standby’ mode. By increasing the drive circuit's output impedance while in ‘standby’ mode, power dissipation due to the termination resistor is reduced. When used in a memory system, additional power savings may be realized by arranging the buffer such that the increased impedance in ‘standby’ mode shifts the signal line voltage so as to avoid the voltage range over which a line receiver's power consumption is greatest.

Abstract: A master-slave flip-flop comprises master and slave latches, with the data output of the master latch connected to the data input of the slave latch. The latches receive clock signals CKM and CKS at their respective clock inputs; each latch is transparent when its clock signal is in a first state and latches a signal applied to its input when its clock signal is in a second state. A clock buffer receives an input clock CKin and generates nominally complementary clock signals CKM and CKS such that one latch is latched while the other is transparent. The clock buffer is arranged to skew CKS with respect to CKM such that the slave latch is made transparent earlier than it would without the skew, making the minimum delay (tpd) between the toggling of CKin and a resulting change at the slave latch's output less than it would otherwise be.

Abstract: An output buffer for driving an AC-coupled resistively terminated transmission line comprises at least first and second drive circuits coupled to an input signal and providing respective drive signals that transition in response to respective transitions of the input signal. The buffer is arranged such that, in response to a given input signal transition, the second drive signal transitions a predetermined amount of time after the first drive signal. The first and second drive signals are summed together to provide the buffer's output signal. The drive circuits are arranged such that the output signal has a first slew rate prior to the transition of the second drive signal, and a second, faster slew rate during the transition of the second drive signal, such that the slew rates reduce ringing that might otherwise occur on the transmission line.

Abstract: An output buffer with a switchable output impedance designed for driving a terminated signal line. The buffer includes a drive circuit, and a means for switching the output impedance of the drive circuit between a first, relatively low output impedance when the output buffer is operated in a ‘normal’ mode, and a second output impedance which is greater than the first output impedance when operated in a ‘standby’ mode. By increasing the drive circuit's output impedance while in ‘standby’ mode, power dissipation due to the termination resistor is reduced. When used in a memory system, additional power savings may be realized by arranging the buffer such that the increased impedance in ‘standby’ mode shifts the signal line voltage so as to avoid the voltage range over which a line receiver's power consumption is greatest.