Patents by Inventor Dhruv Satsangi

Dhruv Satsangi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Side channel attack protection
    Patent number: 11244078
    Abstract: A system for securing a secret word during a read of the secret word from a read-only memory (ROM) is disclosed. The system includes a memory controller coupled to the ROM and a random number generator coupled to the memory controller. The random number generator is configured to generate a random number. The system further includes a number shuffler coupled to the random number generator and the memory controller. The number shuffler is configured to generate a bit read order based on the random number and the memory controller is configured to read bits of the secret word from the ROM according to the bit read order.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: February 8, 2022
    Assignee: NXP USA, INC.
    Inventors: Stefan Doll, Sandeep Jain, Vivek Sharma, Dhruv Satsangi, Arnavesh Varun Giri, Ankur Krishna, Nitin Moudgil
  • Side channel attack protection
    Patent number: 11106830
    Abstract: A system for securing a secret word during a read of the secret word from a read-only memory (ROM) is disclosed. The system includes a memory controller coupled to the ROM and a random number generator coupled to the memory controller. The random number generator is configured to generate a random number. The system further includes a number shuffler coupled to the random number generator and the memory controller. The number shuffler is configured to generate a bit read order based on the random number and the memory controller is configured to read bits of the secret word from the ROM according to the bit read order.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: August 31, 2021
    Assignee: NXP USA, INC.
    Inventors: Stefan Doll, Sandeep Jain, Vivek Sharma, Dhruv Satsangi, Arnavesh Varun Giri, Ankur Krishna, Nitin Moudgil
  • SELF-PROVISIONING AND PROTECTION OF A SECRET KEY
    Publication number: 20200195432
    Abstract: A device is disclosed. The device includes a read-only memory (ROM), a random key generator, a lifecycle controller, an access port and a processor. The processor is configured, based on a lifecycle status, to cause the random key generator to generate a secret key and store the secret key in the ROM. The lifecycle controller is configured to disable an external access via the access port until the secret key is stored in the ROM.
    Type: Application
    Filed: December 14, 2018
    Publication date: June 18, 2020
    Inventors: Stefan Doll, Richard Soja, Sandeep Jain, Pradip Singh, Dhruv Satsangi, Vivek Sharma
  • SIDE CHANNEL ATTACK PROTECTION
    Publication number: 20200184113
    Abstract: A system for securing a secret word during a read of the secret word from a read-only memory (ROM) is disclosed. The system includes a memory controller coupled to the ROM and a random number generator coupled to the memory controller. The random number generator is configured to generate a random number. The system further includes a number shuffler coupled to the random number generator and the memory controller. The number shuffler is configured to generate a bit read order based on the random number and the memory controller is configured to read bits of the secret word from the ROM according to the bit read order.
    Type: Application
    Filed: December 7, 2018
    Publication date: June 11, 2020
    Inventors: Stefan Doll, Sandeep Jain, Vivek Sharma, Dhruv Satsangi, Arnavesh Varun Giri, Ankur Krishna, Nitin Moudgil
  • Memory controller address and data pin multiplexing
    Patent number: 8321649
    Abstract: A system and a method for configuring a memory controller that communicates with a memory device muxes selected pins for the data transfer. The memory controller includes a set of pins where each pin of the set is associated with a data bit and an address bit. A programmable logic block is connected to the set of pins and uses a subset of the set of pins to enable data transfer between the memory device and the memory controller depending on the size of the memory device such that the pins not included in the subset are available for other applications.
    Type: Grant
    Filed: March 18, 2011
    Date of Patent: November 27, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Hemant Nautiyal, Dhruv Satsangi
  • MEMORY CONTROLLER ADDRESS AND DATA PIN MULTIPLEXING
    Publication number: 20120239900
    Abstract: A system and a method for configuring a memory controller that communicates with a memory device muxes selected pins for the data transfer. The memory controller includes a set of pins where each pin of the set is associated with a data bit and an address bit. A programmable logic block is connected to the set of pins and uses a subset of the set of pins to enable data transfer between the memory device and the memory controller depending on the size of the memory device such that the pins not included in the subset are available for other applications.
    Type: Application
    Filed: March 18, 2011
    Publication date: September 20, 2012
    Applicant: FREESCALE SEMICONDUCTOR, INC
    Inventors: Hemant Nautiyal, Dhruv Satsangi