Patents by Inventor Dhruval J. Patel

Dhruval J. Patel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230033277
    Abstract: Techniques for repair of a memory die are disclosed. In the illustrative embodiment, a faulty wordline (or bitline) can be remapped to a redundant wordline on the same layer by entering the address of the faulty wordline in a repair table for the layer. If there are more faulty wordlines on a layer than redundant wordlines available on the layer, the faulty wordlines can be remapped to redundant wordlines on a different layer, and the address of the faulty wordline can be placed in a repair table for the different layer. When a memory operation is received, the wordline address for the memory operation is checked against the repair tables to check if it remapped.
    Type: Application
    Filed: July 30, 2021
    Publication date: February 2, 2023
    Applicant: Intel Corporation
    Inventors: William K. Waller, Dhruval J. Patel, Xiannan Di
  • Patent number: 10903793
    Abstract: Technology for a system operable to regulate an output voltage is described. The system can include an active amplifier configured to amplify an input voltage to produce the output voltage when there is active current consumption at the output voltage of the system. The system can include a standby amplifier configured to switch between amplifying the input voltage for a defined period of time and not amplifying the input voltage for a defined period of time to maintain a desired value for the output voltage of the system.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: January 26, 2021
    Assignee: Intel Corporation
    Inventors: Dhruval J. Patel, Liyao Miao, Matthew Dayley
  • Patent number: 10854245
    Abstract: Techniques to adapt the DC bias of voltage regulators for memory devices as a function of bandwidth demand are described. In one example, a non-volatile memory device includes a plurality of voltage regulator slices, wherein outputs of the plurality of voltage regulators slices are tied together to provide a voltage to perform operations on the array. The voltage regulator slices can be enabled or disabled based on a signal from a memory controller, such as an indication of an upcoming change in bandwidth demand for a rank including the memory device.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: December 1, 2020
    Assignee: Intel Corporation
    Inventors: Setul M. Shah, William Sheung, Dhruval J. Patel
  • Publication number: 20190006993
    Abstract: Technology for a system operable to regulate an output voltage is described. The system can include an active amplifier configured to amplify an input voltage to produce the output voltage when there is active current consumption at the output voltage of the system. The system can include a standby amplifier configured to switch between amplifying the input voltage for a defined period of time and not amplifying the input voltage for a defined period of time to maintain a desired value for the output voltage of the system.
    Type: Application
    Filed: June 30, 2017
    Publication date: January 3, 2019
    Applicant: Intel Corporation
    Inventors: Dhruval J. Patel, Liyao Miao, Matthew G. Dayley