Abstract: A memory is provided with a pair of banks including a first bank of bitcells and a second bank of bitcells. An I/O circuit for the pair of banks includes a shared write path configured to couple a write driver input signal to the first bank of bitcells responsive to an assertion of a write enable signal for the first bank of bitcells and to couple the write driver input signal to the second bank of bitcells responsive to an assertion of a write enable signal for the second bank of bitcells. The I/O circuit also includes a shared read path configured to couple a data bit output signal from the first bank of bitcells to a sense amplifier responsive to a de-assertion of the write enable signal for the first bank of bitcells and to couple a data bit output signal from the second bank of bitcells to the sense amplifier responsive to a de-assertion of the write enable signal for the second bank of bitcells.

Abstract: A memory is provided with a plurality of column groups and two redundant column groups. If there are two defective columns in the plurality of column groups, the plurality of column groups may be divided into a no-shift region, a one-shift region, and a two-shift region. The memory includes a plurality of input/output circuits corresponding to the plurality of column groups. Each input/output circuit may provide a data input signal during a write operation and receive a data output signal during a read operation. Each input/output circuit also includes a switch matrix. In the no-shift region, the switch matrix couples the input/output circuit to a core in the corresponding column group. In the one-shift region, the switch matrix couples the input/output circuit to a core in a subsequent column group. In the two-shift region, the switch matrix couples the input/output circuit to a core in a next-to-subsequent column group.

Abstract: A memory is provided that includes bitcell VDD boosting to increase a read margin. In some implementations, the positive boost for the bitcell VDD may be provided by a capacitor that is also used for negative boosting of a write driver.

Abstract: A memory is provided with a plurality of column groups and two redundant column groups. If there are two defective columns in the plurality of column groups, the plurality of column groups may be divided into a no-shift region, a one-shift region, and a two-shift region. The memory includes a plurality of input/output circuits corresponding to the plurality of column groups. Each input/output circuit may provide a data input signal during a write operation and receive a data output signal during a read operation. Each input/output circuit also includes a switch matrix. In the no-shift region, the switch matrix couples the input/output circuit to a core in the corresponding column group. In the one-shift region, the switch matrix couples the input/output circuit to a core in a subsequent column group. In the two-shift region, the switch matrix couples the input/output circuit to a core in a next-to-subsequent column group.

Abstract: A memory is provided that includes a self-timed memory circuit that controls the isolation of a sense amplifier from a column selected by a column multiplexer until the completion of a bit line voltage difference development delay. The self-timed memory circuit also controls the release of a pre-charge for the sense amplifier responsive to the completion of the bit line voltage difference development delay.

Abstract: A memory is provided with a plurality of column groups and two redundant column groups. If there are two defective columns in the plurality of column groups, the plurality of column groups may be divided into a no-shift region, a one-shift region, and a two-shift region. The memory includes a plurality of input/output circuits corresponding to the plurality of column groups. Each input/output circuit may provide a data input signal during a write operation and receive a data output signal during a read operation. Each input/output circuit also includes a switch matrix. In the no-shift region, the switch matrix couples the input/output circuit to a core in the corresponding column group. In the one-shift region, the switch matrix couples the input/output circuit to a core in a subsequent column group. In the two-shift region, the switch matrix couples the input/output circuit to a core in a next-to-subsequent column group.

Abstract: A memory is provided that includes bitcell VDD boosting to increase a read margin. In some implementations, the positive boost for the bitcell VDD may be provided by a capacitor that is also used for negative boosting of a write driver.

Abstract: A memory is provided that includes a self-timed memory circuit that controls the isolation of a sense amplifier from a column selected by a column multiplexer until the completion of a bit line voltage difference development delay. The self-timed memory circuit also controls the release of a pre-charge for the sense amplifier responsive to the completion of the bit line voltage difference development delay.

Abstract: A memory is provided that includes a write multiplexer, which multiplexes among a plurality of bit line columns. The multiplexer includes a positive boost circuit that applies a positive boost to a voltage at the gates of transistors to strengthen an on state of those transistors. The positive boosting may be in addition to, or instead of, negative boosting at a write driver circuit.

Abstract: A memory device including: a first core of memory bitcells; a second core of memory bitcells; pre-decoding circuitry shared by the first core and the second core; and a row decoder coupled to the pre-decoding circuitry, the first core, and the second core, the row decoder including a first set-reset (SR) latch coupled to a first wordline of the first core and a second SR latch coupled to a second wordline of the second core.