Patents by Inventor Di-An Hong

Di-An Hong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160200741
    Abstract: The invention provides novel compounds having the general formula: wherein R1, R2, R3, R4, R5, R7, A1, A2 and A3 are as described herein, compositions including the compounds and methods of using the compounds.
    Type: Application
    Filed: November 18, 2015
    Publication date: July 14, 2016
    Applicant: Hoffmann-La Roche Inc.
    Inventors: Song FENG, LU GAO, Di HONG, Lisha WANG, Hongying YUN, Shu-Hai ZHAO
  • Patent number: 9206191
    Abstract: The invention provides novel compounds having the general formula: wherein R1, R2, R3, R4, R5, R7, A1, A2 and A3 are as described herein, compositions including the compounds and methods of using the compounds.
    Type: Grant
    Filed: January 9, 2015
    Date of Patent: December 8, 2015
    Assignee: Hoffmann-La Roche Inc.
    Inventors: Song Feng, Lu Gao, Di Hong, Lisha Wang, Hongying Yun, Shu-Hai Zhao
  • Publication number: 20150158879
    Abstract: The invention provides novel compounds having the general formula: wherein R1, R2, R3, R4, R5, R7, A1, A2 and A3 are as described herein, compositions including the compounds and methods of using the compounds.
    Type: Application
    Filed: January 9, 2015
    Publication date: June 11, 2015
    Applicant: Hoffmann-La Roche Inc.
    Inventors: Song Feng, Lu Gao, Di Hong, Lisha Wang, Hongying Yun, Shu-Hai Zhao
  • Patent number: 8865539
    Abstract: An integrated circuit comprises a substrate and a buried dielectric formed in the substrate. The buried dielectric has a first thickness in a first region, a second buried dielectric thickness in a second region, and a step between the first and second regions. A semiconductor layer overlies the buried dielectric.
    Type: Grant
    Filed: May 4, 2011
    Date of Patent: October 21, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Yu Chen, Chang-Yun Chang, Di-Hong Lee, Fu-Liang Yang
  • Publication number: 20110212579
    Abstract: An integrated circuit comprises a substrate and a buried dielectric formed in the substrate. The buried dielectric has a first thickness in a first region, a second buried dielectric thickness in a second region, and a step between the first and second regions. A semiconductor layer overlies the buried dielectric.
    Type: Application
    Filed: May 4, 2011
    Publication date: September 1, 2011
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Yu Chen, Chang-Yun Chang, Di-Hong Lee, Fu-Liang Yang
  • Patent number: 7983426
    Abstract: A method for monitoring and reporting sound pressure level exposure for a user of a first communication device (104) is implemented in one embodiment when the device measures a sound pressure level (SPL) of the surrounding environment. The device stores at least the SPL measurement in a memory, producing an SPL exposure record, and displays a visual representation of the SPL exposure record on a display screen (212). In another embodiment, the SPL is measured by a second communication device (102) and combined with a known SPL for an output audio transducer (306) of the second device, producing a user sound exposure level. The user sound exposure level is transmitted to the first communication device. The user is notified when the user sound exposure level exceeds a predetermined threshold. A server (112) may also be used to track SPLs over time and recommend corrective action when exposure limits are exceeded.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: July 19, 2011
    Assignee: Motorola Mobility, Inc.
    Inventors: Francesca Schuler, Di-An Hong, Krishna D. Jonnalagadda, Kaustubh R. Kale, Alif Khawand, Jose C. Lacal, Padmaja Ramadas
  • Patent number: 7663185
    Abstract: A fin-FET device and a method for fabrication thereof both employ a bulk semiconductor substrate. A fin and an adjoining trough are formed within the bulk semiconductor substrate. The trough is partially backfilled with a deposited dielectric layer to form an exposed fin region and an unexposed fin region. A gate dielectric layer is formed upon the exposed fin region and a gate electrode is formed upon the gate dielectric layer. By employing a bulk semiconductor substrate the fin-FET device is fabricated cost effectively.
    Type: Grant
    Filed: May 27, 2006
    Date of Patent: February 16, 2010
    Assignee: Taiwan Semiconductor Manufacturing Co, Ltd
    Inventors: Kuang-Hsin Chen, Hsun-Chih Tsao, Jhi-Cherng Lu, Chuan-Ping Hou, Peng-Fu Hsu, Hung-Wei Chen, Di-Hong Lee
  • Patent number: 7538351
    Abstract: A semiconductor device and method for forming the same including improved electrostatic discharge protection for advanced semiconductor devices, the semiconductor device including providing semiconductor substrate having a pre-selected surface orientation and crystal direction; an insulator layer overlying the semiconductor substrate; a first semiconductor active region overlying the insulator layer having a first surface orientation selected from the group consisting of <100> and <110>; a second semiconductor active region extending through a thickness portion of the insulator layer having a second surface orientation selected from the group consisting of <110> and <100> different from the first surface orientation; wherein MOS devices including a first MOS device of a first conduction type is disposed on the first semiconductor active region and a second MOS device of a second conduction type is disposed on the second semiconductor active region.
    Type: Grant
    Filed: March 23, 2005
    Date of Patent: May 26, 2009
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung-Wei Chen, Hsun-Chih Tsao, Kuang-Hsin Chen, Di-Hong Lee
  • Publication number: 20090054752
    Abstract: A photoplethysmographic sensing system for determining a user's pulse rate includes a light emitting device (100, 201, 310, 500) including a first plurality of light emitting particles (108, 208, 317) having a first diameter and emitting light having a first wavelength. A detector (118, 218, 500) is positioned to receive light emitted from the plurality of light emitting particles (108, 208, 317) and a processing device (500) determines the pulse rate. The light emitting device (100, 201, 310, 500) and the detector (118, 218, 500) are disposed on a flexible polymeric material (102, 202, 334). The light emitting device (100, 201, 310, 500) may include a second plurality of light emitting particles (108, 208, 317) having a second diameter and emitting light having a second wavelength, wherein the processing device (500) determines the user's blood oxygen level. The light emitting particles (108, 208, 317) may comprise one of quantum dots, electroluminescent particles, or organic particles.
    Type: Application
    Filed: August 22, 2007
    Publication date: February 26, 2009
    Applicant: MOTOROLA, INC.
    Inventors: Krishna Jonnalagadda, Di-An Hong, Xun Luo, Francesca Schuler, Andrew Skipor
  • Patent number: 7452778
    Abstract: Nano-wires, preferably of less than 20 nm diameter, can be formed with minimized risk of narrowing and breaking that results from silicon atom migration during an annealing process step. This is accomplished by masking portion of the active layer where silicon atomer would otherwise agglomerate with a material such as silicon dioxide, silicon nitride, or other dielectric that eliminates or substantially reduces the silicon atom migration. Nano-wires, nanotubes, nano-rods, and other features can be formed and can optionally be incorporated into devices, such as by use as a channel region in a transistor device.
    Type: Grant
    Filed: April 12, 2005
    Date of Patent: November 18, 2008
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Wei Chen, Yee-Chia Yeo, Di-Hong Lee, Fu-Liang Yang, Chenming Hu
  • Publication number: 20080237717
    Abstract: An integrated circuit comprises a substrate and a buried dielectric formed in the substrate. The buried dielectric has a first thickness in a first region, a second buried dielectric thickness in a second region, and a step between the first and second regions. A semiconductor layer overlies the buried dielectric.
    Type: Application
    Filed: April 25, 2008
    Publication date: October 2, 2008
    Inventors: Hao-Yu Chen, Chang-Yun Chang, Di-Hong Lee, Fu-Liang Yang
  • Publication number: 20080159547
    Abstract: A method for monitoring and reporting sound pressure level exposure for a user of a first communication device (104) is implemented in one embodiment when the device measures a sound pressure level (SPL) of the surrounding environment. The device stores at least the SPL measurement in a memory, producing an SPL exposure record, and displays a visual representation of the SPL exposure record on a display screen (212). In another embodiment, the SPL is measured by a second communication device (102) and combined with a known SPL for an output audio transducer (306) of the second device, producing a user sound exposure level. The user sound exposure level is transmitted to the first communication device. The user is notified when the user sound exposure level exceeds a predetermined threshold. A server (112) may also be used to track SPLs over time and recommend corrective action when exposure limits are exceeded.
    Type: Application
    Filed: December 29, 2006
    Publication date: July 3, 2008
    Inventors: Francesca Schuler, Di-An Hong, Krishna D. Jonnalagadda, Kaustubh R. Kale, Alif Khawand, Jose C. Lacal, Padmaja Ramadas
  • Publication number: 20080132798
    Abstract: A multi-functional wireless headset may include a heart rate sensing assembly configured to detect heart rate data of a wearer of the headset, and a wireless communication unit configured to communicate heart rate data to a gateway device.
    Type: Application
    Filed: November 30, 2006
    Publication date: June 5, 2008
    Applicant: Motorola, Inc
    Inventors: Di-An Hong, Mark W. Cholewczynski, Janice M. Danvir, Krishna D. Jonnalagadda, Francesca Schuler
  • Patent number: 7382023
    Abstract: An integrated circuit comprises a substrate and a buried dielectric formed in the substrate. The buried dielectric has a first thickness in a first region, a second buried dielectric thickness in a second region, and a step between the first and second regions. A semiconductor layer overlies the buried dielectric.
    Type: Grant
    Filed: March 29, 2005
    Date of Patent: June 3, 2008
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Yu Chen, Chang-Yun Chang, Di-Hong Lee, Fu-Liang Yang
  • Publication number: 20080103701
    Abstract: Software (100, 600, 1000, 1100) for automatically designing and optimizing signal processing networks (e.g., 200, 700, 800, 900) is provided. The software use genetic programming e.g., gene expression programming in combination with numerical optimization, e.g., a hybrid differential evolution/genetic algorithm numerical optimization to design and optimize signal processing networks.
    Type: Application
    Filed: October 31, 2006
    Publication date: May 1, 2008
    Applicant: MOTOROLA, INC.
    Inventors: Weimin Xiao, Di-An Hong, Magdi A. Mohamed, Chi Zhou
  • Patent number: 7332777
    Abstract: In a method of manufacturing a semiconductor device, an initial structure is provided. The initial structure includes a substrate, a patterned silicon layer, and a covering layer. The substrate has a buried insulator layer formed thereon. The patterned silicon layer is formed on the buried insulator layer. The covering layer is formed on the patterned silicon layer. A first layer is formed on the initial structure. Part of the first layer is removed with an etching process, such that a sidewall portion of the patterned silicon layer is exposed and such that a remaining portion of the first layer remains at a corner where the patterned silicon layer interfaces with the buried insulator layer. An oxide liner is formed on the exposed sidewall portion. A recess may be formed in the buried insulator layer (prior to forming the first layer) and may extend partially beneath the patterned silicon layer.
    Type: Grant
    Filed: September 7, 2005
    Date of Patent: February 19, 2008
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuang-Hsin Chen, Hsun-Chih Tsao, Hung-Wei Chen, Di-Hong Lee, Chuan-Ping Hou, Jhi-Cherng Lu
  • Publication number: 20070272954
    Abstract: A fin-FET device and a method for fabrication thereof both employ a bulk semiconductor substrate. A fin and an adjoining trough are formed within the bulk semiconductor substrate. The trough is partially backfilled with a deposited dielectric layer to form an exposed fin region and an unexposed fin region. A gate dielectric layer is formed upon the exposed fin region and a gate electrode is formed upon the gate dielectric layer. By employing a bulk semiconductor substrate the fin-FET device is fabricated cost effectively.
    Type: Application
    Filed: May 27, 2006
    Publication date: November 29, 2007
    Inventors: Kuang-Hsin Chen, Hsun-Chih Tsao, Jhi-Cherng Lu, Chuan-Ping Hou, Peng-Fu Hsu, Hung-Wei Chen, Di-Hong Lee
  • Patent number: 7265425
    Abstract: A semiconductor device formed on a semiconductor substrate and a method of forming the same. In one embodiment, the semiconductor device includes a gate over the semiconductor substrate and a dielectric liner on a sidewall of the gate. The semiconductor device also includes an extension spacer adjacent and extending laterally beyond the dielectric liner along the semiconductor substrate. The semiconductor device further includes a source/drain located below an upper surface of the semiconductor substrate and adjacent a channel region under the gate. The source/drain extends under the dielectric liner and the extension spacer. The semiconductor device still further includes a silicide region over a portion of the source/drain and extending laterally beyond the extension spacer along the semiconductor substrate. Thus, the extension spacer is interposed between the dielectric liner and the silicide region located over a portion of the source/drain.
    Type: Grant
    Filed: November 15, 2004
    Date of Patent: September 4, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuang-Hsin Chen, Tang-Xuan Zhong, Chien-Chao Huang, Cheng-Kuo Wen, Di-Hong Lee
  • Patent number: 7205601
    Abstract: A FinFET split gate EEPROM structure includes a semiconductor substrate and an elongated semiconductor fin extending above the substrate. A control gate straddles the fin, the fin's sides and a first drain-proximate portion of a channel between a source and drain in the fin. The control gate includes a tunnel layer and a floating electrode over which are a first insulative stratum and a first conductive stratum. A select gate straddles the fin and its sides and a second, source-promixate portion of the channel. The select gate includes a second insulative stratum and a second conductive stratum. The insulative strata are portions of a continuous insulative layer covering the substrate and the fin. The conductive strata are electrically continuous portions of a continuous conductive layer formed on the insulative layer.
    Type: Grant
    Filed: June 9, 2005
    Date of Patent: April 17, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Di-Hong Lee, Hsun-Chih Tsao, Kuang-Hsin Chen, Hung-Wei Chen
  • Publication number: 20060278915
    Abstract: A FinFET split gate EEPROM structure includes a semiconductor substrate and an elongated semiconductor fin extending above the substrate. A control gate straddles the fin, the fin's sides and a first drain-proximate portion of a channel between a source and drain in the fin. The control gate includes a tunnel layer and a floating electrode over which are a first insulative stratum and a first conductive stratum. A select gate straddles the fin and its sides and a second, source-promixate portion of the channel. The select gate includes a second insulative stratum and a second conductive stratum. The insulative strata are portions of a continuous insulative layer covering the substrate and the fin. The conductive strata are electrically continuous portions of a continuous conductive layer formed on the insulative layer.
    Type: Application
    Filed: June 9, 2005
    Publication date: December 14, 2006
    Inventors: Di-Hong Lee, Hsun-Chih Tsao, Kuang-Hsin Chen, Hung-Wei Chen