Patents by Inventor Di-An Hong

Di-An Hong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240114936
    Abstract: The present disclosure provides a preparation method of an easy-to-cook whole grain based on microwave-induced cracking, and belongs to the technical field of food processing. In the present disclosure, the preparation method of an easy-to-cook whole grain includes the following steps: subjecting a whole grain to a heat-moisture treatment, and conducting short-time microwave-induced cracking, tempering, and cooling to obtain the easy-to-cook whole grain. The easy-to-cook whole grain obtained by the preparation method of the present disclosure has a complete grain, a slightly-expanded volume, and fine cracks on its surface. Compared with unprocessed whole grains, the easy-to-cook whole grain has a water absorption increased from 1.35 times to 1.9 times an original weight of the unprocessed whole grains during rice steaming.
    Type: Application
    Filed: September 8, 2023
    Publication date: April 11, 2024
    Inventors: Shuwen LU, Chuanying REN, Bin HONG, Shan ZHANG, Dixin SHA, Junran FENG, Di YUAN, Bo LI
  • Patent number: 11908239
    Abstract: The disclosure provides an image recognition network model training method, including: acquiring a first image feature corresponding to an image set; acquiring a first identity prediction result by using an identity classifier, and acquiring a first pose prediction result by using a pose classifier; obtaining an identity classifier according to the first identity prediction result and an identity tag, and obtaining a pose classifier according to the first pose prediction result and a pose tag; performing pose transformation on the first image feature by using a generator, to obtain a second image feature corresponding to the image set; acquiring a second identity prediction result by using the identity classifier, and acquiring a second pose prediction result by using the pose classifier; and training the generator.
    Type: Grant
    Filed: May 13, 2021
    Date of Patent: February 20, 2024
    Assignee: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED
    Inventors: Zheng Ge, Ze Qun Jie, Hao Wang, Zhi Feng Li, Di Hong Gong, Wei Liu
  • Publication number: 20230334905
    Abstract: A face recognition method includes: extracting a first identity feature of a first face image by using a feature extraction module, and extracting a second identity feature of a second face image by using the feature extraction module, wherein the feature extraction module is implemented by using a neural network, and pre-trained in a manner such that a correlation coefficient of training batch data is obtained based on an identity feature and an age feature of a sample face image in the training batch data, and decorrelated training of the identity feature and the age feature is performed on the feature extraction module based on the correlation coefficient; and performing a face recognition based on determining a similarity between faces in the first face image and the second face image according to the first identity feature and the second identity feature.
    Type: Application
    Filed: June 20, 2023
    Publication date: October 19, 2023
    Applicant: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED
    Inventors: Hao WANG, Di Hong Gong, Zhi Feng Li, Wei Liu
  • Patent number: 11763599
    Abstract: A face recognition method includes: extracting a first identity feature of a first face image by using a feature extraction module, and extracting a second identity feature of a second face image by using the feature extraction module, wherein the feature extraction module is implemented by using a neural network, and pre-trained in a manner such that a correlation coefficient of training batch data is obtained based on an identity feature and an age feature of a sample face image in the training batch data, and decorrelated training of the identity feature and the age feature is performed on the feature extraction module based on the correlation coefficient; and performing a face recognition based on determining a similarity between faces in the first face image and the second face image according to the first identity feature and the second identity feature.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: September 19, 2023
    Assignee: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED
    Inventors: Hao Wang, Di Hong Gong, Zhi Feng Li, Wei Liu
  • Publication number: 20220139866
    Abstract: A method for manufacturing a semiconductor package structure and a semiconductor manufacturing apparatus are provided. The method includes: (a) providing a package body disposed on a chuck, wherein the package body includes at least one semiconductor element encapsulated in an encapsulant; and (b) sucking the package body through the chuck to create a plurality of negative pressures on a bottom surface of the package body sequentially from an inner portion to an outer portion of the package body.
    Type: Application
    Filed: October 30, 2020
    Publication date: May 5, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Yun Di HONG
  • Publication number: 20220139751
    Abstract: A method for manufacturing a semiconductor package structure and a clamp apparatus are provided. The method includes: (a) providing a package body disposed on a chuck, wherein the package body includes at least one semiconductor element encapsulated in an encapsulant; (b) moving a pressing tool transversely to above the package body; and (c) pressing the package body on the chuck through the pressing tool.
    Type: Application
    Filed: October 30, 2020
    Publication date: May 5, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Yun Di HONG
  • Publication number: 20210264136
    Abstract: A face recognition method includes: extracting a first identity feature of a first face image by using a feature extraction module, and extracting a second identity feature of a second face image by using the feature extraction module, wherein the feature extraction module is implemented by using a neural network, and pre-trained in a manner such that a correlation coefficient of training batch data is obtained based on an identity feature and an age feature of a sample face image in the training batch data, and decorrelated training of the identity feature and the age feature is performed on the feature extraction module based on the correlation coefficient; and performing a face recognition based on determining a similarity between faces in the first face image and the second face image according to the first identity feature and the second identity feature.
    Type: Application
    Filed: May 7, 2021
    Publication date: August 26, 2021
    Applicant: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED
    Inventors: Hao Wang, Di Hong Gong, Zhi Feng Li, Wei Liu
  • Publication number: 20210264205
    Abstract: The disclosure provides an image recognition network model training method, including: acquiring a first image feature corresponding to an image set; acquiring a first identity prediction result by using an identity classifier, and acquiring a first pose prediction result by using a pose classifier; obtaining an identity classifier according to the first identity prediction result and an identity tag, and obtaining a pose classifier according to the first pose prediction result and a pose tag; performing pose transformation on the first image feature by using a generator, to obtain a second image feature corresponding to the image set; acquiring a second identity prediction result by using the identity classifier, and acquiring a second pose prediction result by using the pose classifier; and training the generator.
    Type: Application
    Filed: May 13, 2021
    Publication date: August 26, 2021
    Applicant: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED
    Inventors: Zheng Ge, Ze Qun Jie, Hao Wang, Zhi Feng Li, Di Hong Gong, Wei Liu
  • Publication number: 20160200741
    Abstract: The invention provides novel compounds having the general formula: wherein R1, R2, R3, R4, R5, R7, A1, A2 and A3 are as described herein, compositions including the compounds and methods of using the compounds.
    Type: Application
    Filed: November 18, 2015
    Publication date: July 14, 2016
    Applicant: Hoffmann-La Roche Inc.
    Inventors: Song FENG, LU GAO, Di HONG, Lisha WANG, Hongying YUN, Shu-Hai ZHAO
  • Patent number: 9206191
    Abstract: The invention provides novel compounds having the general formula: wherein R1, R2, R3, R4, R5, R7, A1, A2 and A3 are as described herein, compositions including the compounds and methods of using the compounds.
    Type: Grant
    Filed: January 9, 2015
    Date of Patent: December 8, 2015
    Assignee: Hoffmann-La Roche Inc.
    Inventors: Song Feng, Lu Gao, Di Hong, Lisha Wang, Hongying Yun, Shu-Hai Zhao
  • Publication number: 20150158879
    Abstract: The invention provides novel compounds having the general formula: wherein R1, R2, R3, R4, R5, R7, A1, A2 and A3 are as described herein, compositions including the compounds and methods of using the compounds.
    Type: Application
    Filed: January 9, 2015
    Publication date: June 11, 2015
    Applicant: Hoffmann-La Roche Inc.
    Inventors: Song Feng, Lu Gao, Di Hong, Lisha Wang, Hongying Yun, Shu-Hai Zhao
  • Patent number: 8865539
    Abstract: An integrated circuit comprises a substrate and a buried dielectric formed in the substrate. The buried dielectric has a first thickness in a first region, a second buried dielectric thickness in a second region, and a step between the first and second regions. A semiconductor layer overlies the buried dielectric.
    Type: Grant
    Filed: May 4, 2011
    Date of Patent: October 21, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Yu Chen, Chang-Yun Chang, Di-Hong Lee, Fu-Liang Yang
  • Publication number: 20110212579
    Abstract: An integrated circuit comprises a substrate and a buried dielectric formed in the substrate. The buried dielectric has a first thickness in a first region, a second buried dielectric thickness in a second region, and a step between the first and second regions. A semiconductor layer overlies the buried dielectric.
    Type: Application
    Filed: May 4, 2011
    Publication date: September 1, 2011
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Yu Chen, Chang-Yun Chang, Di-Hong Lee, Fu-Liang Yang
  • Patent number: 7983426
    Abstract: A method for monitoring and reporting sound pressure level exposure for a user of a first communication device (104) is implemented in one embodiment when the device measures a sound pressure level (SPL) of the surrounding environment. The device stores at least the SPL measurement in a memory, producing an SPL exposure record, and displays a visual representation of the SPL exposure record on a display screen (212). In another embodiment, the SPL is measured by a second communication device (102) and combined with a known SPL for an output audio transducer (306) of the second device, producing a user sound exposure level. The user sound exposure level is transmitted to the first communication device. The user is notified when the user sound exposure level exceeds a predetermined threshold. A server (112) may also be used to track SPLs over time and recommend corrective action when exposure limits are exceeded.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: July 19, 2011
    Assignee: Motorola Mobility, Inc.
    Inventors: Francesca Schuler, Di-An Hong, Krishna D. Jonnalagadda, Kaustubh R. Kale, Alif Khawand, Jose C. Lacal, Padmaja Ramadas
  • Patent number: 7663185
    Abstract: A fin-FET device and a method for fabrication thereof both employ a bulk semiconductor substrate. A fin and an adjoining trough are formed within the bulk semiconductor substrate. The trough is partially backfilled with a deposited dielectric layer to form an exposed fin region and an unexposed fin region. A gate dielectric layer is formed upon the exposed fin region and a gate electrode is formed upon the gate dielectric layer. By employing a bulk semiconductor substrate the fin-FET device is fabricated cost effectively.
    Type: Grant
    Filed: May 27, 2006
    Date of Patent: February 16, 2010
    Assignee: Taiwan Semiconductor Manufacturing Co, Ltd
    Inventors: Kuang-Hsin Chen, Hsun-Chih Tsao, Jhi-Cherng Lu, Chuan-Ping Hou, Peng-Fu Hsu, Hung-Wei Chen, Di-Hong Lee
  • Patent number: 7538351
    Abstract: A semiconductor device and method for forming the same including improved electrostatic discharge protection for advanced semiconductor devices, the semiconductor device including providing semiconductor substrate having a pre-selected surface orientation and crystal direction; an insulator layer overlying the semiconductor substrate; a first semiconductor active region overlying the insulator layer having a first surface orientation selected from the group consisting of <100> and <110>; a second semiconductor active region extending through a thickness portion of the insulator layer having a second surface orientation selected from the group consisting of <110> and <100> different from the first surface orientation; wherein MOS devices including a first MOS device of a first conduction type is disposed on the first semiconductor active region and a second MOS device of a second conduction type is disposed on the second semiconductor active region.
    Type: Grant
    Filed: March 23, 2005
    Date of Patent: May 26, 2009
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung-Wei Chen, Hsun-Chih Tsao, Kuang-Hsin Chen, Di-Hong Lee
  • Publication number: 20090054752
    Abstract: A photoplethysmographic sensing system for determining a user's pulse rate includes a light emitting device (100, 201, 310, 500) including a first plurality of light emitting particles (108, 208, 317) having a first diameter and emitting light having a first wavelength. A detector (118, 218, 500) is positioned to receive light emitted from the plurality of light emitting particles (108, 208, 317) and a processing device (500) determines the pulse rate. The light emitting device (100, 201, 310, 500) and the detector (118, 218, 500) are disposed on a flexible polymeric material (102, 202, 334). The light emitting device (100, 201, 310, 500) may include a second plurality of light emitting particles (108, 208, 317) having a second diameter and emitting light having a second wavelength, wherein the processing device (500) determines the user's blood oxygen level. The light emitting particles (108, 208, 317) may comprise one of quantum dots, electroluminescent particles, or organic particles.
    Type: Application
    Filed: August 22, 2007
    Publication date: February 26, 2009
    Applicant: MOTOROLA, INC.
    Inventors: Krishna Jonnalagadda, Di-An Hong, Xun Luo, Francesca Schuler, Andrew Skipor
  • Patent number: 7452778
    Abstract: Nano-wires, preferably of less than 20 nm diameter, can be formed with minimized risk of narrowing and breaking that results from silicon atom migration during an annealing process step. This is accomplished by masking portion of the active layer where silicon atomer would otherwise agglomerate with a material such as silicon dioxide, silicon nitride, or other dielectric that eliminates or substantially reduces the silicon atom migration. Nano-wires, nanotubes, nano-rods, and other features can be formed and can optionally be incorporated into devices, such as by use as a channel region in a transistor device.
    Type: Grant
    Filed: April 12, 2005
    Date of Patent: November 18, 2008
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Wei Chen, Yee-Chia Yeo, Di-Hong Lee, Fu-Liang Yang, Chenming Hu
  • Publication number: 20080237717
    Abstract: An integrated circuit comprises a substrate and a buried dielectric formed in the substrate. The buried dielectric has a first thickness in a first region, a second buried dielectric thickness in a second region, and a step between the first and second regions. A semiconductor layer overlies the buried dielectric.
    Type: Application
    Filed: April 25, 2008
    Publication date: October 2, 2008
    Inventors: Hao-Yu Chen, Chang-Yun Chang, Di-Hong Lee, Fu-Liang Yang
  • Publication number: 20080159547
    Abstract: A method for monitoring and reporting sound pressure level exposure for a user of a first communication device (104) is implemented in one embodiment when the device measures a sound pressure level (SPL) of the surrounding environment. The device stores at least the SPL measurement in a memory, producing an SPL exposure record, and displays a visual representation of the SPL exposure record on a display screen (212). In another embodiment, the SPL is measured by a second communication device (102) and combined with a known SPL for an output audio transducer (306) of the second device, producing a user sound exposure level. The user sound exposure level is transmitted to the first communication device. The user is notified when the user sound exposure level exceeds a predetermined threshold. A server (112) may also be used to track SPLs over time and recommend corrective action when exposure limits are exceeded.
    Type: Application
    Filed: December 29, 2006
    Publication date: July 3, 2008
    Inventors: Francesca Schuler, Di-An Hong, Krishna D. Jonnalagadda, Kaustubh R. Kale, Alif Khawand, Jose C. Lacal, Padmaja Ramadas