Patents by Inventor Di-Hong Lee
Di-Hong Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8865539Abstract: An integrated circuit comprises a substrate and a buried dielectric formed in the substrate. The buried dielectric has a first thickness in a first region, a second buried dielectric thickness in a second region, and a step between the first and second regions. A semiconductor layer overlies the buried dielectric.Type: GrantFiled: May 4, 2011Date of Patent: October 21, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hao-Yu Chen, Chang-Yun Chang, Di-Hong Lee, Fu-Liang Yang
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Publication number: 20110212579Abstract: An integrated circuit comprises a substrate and a buried dielectric formed in the substrate. The buried dielectric has a first thickness in a first region, a second buried dielectric thickness in a second region, and a step between the first and second regions. A semiconductor layer overlies the buried dielectric.Type: ApplicationFiled: May 4, 2011Publication date: September 1, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hao-Yu Chen, Chang-Yun Chang, Di-Hong Lee, Fu-Liang Yang
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Patent number: 7663185Abstract: A fin-FET device and a method for fabrication thereof both employ a bulk semiconductor substrate. A fin and an adjoining trough are formed within the bulk semiconductor substrate. The trough is partially backfilled with a deposited dielectric layer to form an exposed fin region and an unexposed fin region. A gate dielectric layer is formed upon the exposed fin region and a gate electrode is formed upon the gate dielectric layer. By employing a bulk semiconductor substrate the fin-FET device is fabricated cost effectively.Type: GrantFiled: May 27, 2006Date of Patent: February 16, 2010Assignee: Taiwan Semiconductor Manufacturing Co, LtdInventors: Kuang-Hsin Chen, Hsun-Chih Tsao, Jhi-Cherng Lu, Chuan-Ping Hou, Peng-Fu Hsu, Hung-Wei Chen, Di-Hong Lee
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Patent number: 7538351Abstract: A semiconductor device and method for forming the same including improved electrostatic discharge protection for advanced semiconductor devices, the semiconductor device including providing semiconductor substrate having a pre-selected surface orientation and crystal direction; an insulator layer overlying the semiconductor substrate; a first semiconductor active region overlying the insulator layer having a first surface orientation selected from the group consisting of <100> and <110>; a second semiconductor active region extending through a thickness portion of the insulator layer having a second surface orientation selected from the group consisting of <110> and <100> different from the first surface orientation; wherein MOS devices including a first MOS device of a first conduction type is disposed on the first semiconductor active region and a second MOS device of a second conduction type is disposed on the second semiconductor active region.Type: GrantFiled: March 23, 2005Date of Patent: May 26, 2009Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hung-Wei Chen, Hsun-Chih Tsao, Kuang-Hsin Chen, Di-Hong Lee
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Patent number: 7452778Abstract: Nano-wires, preferably of less than 20 nm diameter, can be formed with minimized risk of narrowing and breaking that results from silicon atom migration during an annealing process step. This is accomplished by masking portion of the active layer where silicon atomer would otherwise agglomerate with a material such as silicon dioxide, silicon nitride, or other dielectric that eliminates or substantially reduces the silicon atom migration. Nano-wires, nanotubes, nano-rods, and other features can be formed and can optionally be incorporated into devices, such as by use as a channel region in a transistor device.Type: GrantFiled: April 12, 2005Date of Patent: November 18, 2008Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Wei Chen, Yee-Chia Yeo, Di-Hong Lee, Fu-Liang Yang, Chenming Hu
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Publication number: 20080237717Abstract: An integrated circuit comprises a substrate and a buried dielectric formed in the substrate. The buried dielectric has a first thickness in a first region, a second buried dielectric thickness in a second region, and a step between the first and second regions. A semiconductor layer overlies the buried dielectric.Type: ApplicationFiled: April 25, 2008Publication date: October 2, 2008Inventors: Hao-Yu Chen, Chang-Yun Chang, Di-Hong Lee, Fu-Liang Yang
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Patent number: 7382023Abstract: An integrated circuit comprises a substrate and a buried dielectric formed in the substrate. The buried dielectric has a first thickness in a first region, a second buried dielectric thickness in a second region, and a step between the first and second regions. A semiconductor layer overlies the buried dielectric.Type: GrantFiled: March 29, 2005Date of Patent: June 3, 2008Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hao-Yu Chen, Chang-Yun Chang, Di-Hong Lee, Fu-Liang Yang
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Patent number: 7332777Abstract: In a method of manufacturing a semiconductor device, an initial structure is provided. The initial structure includes a substrate, a patterned silicon layer, and a covering layer. The substrate has a buried insulator layer formed thereon. The patterned silicon layer is formed on the buried insulator layer. The covering layer is formed on the patterned silicon layer. A first layer is formed on the initial structure. Part of the first layer is removed with an etching process, such that a sidewall portion of the patterned silicon layer is exposed and such that a remaining portion of the first layer remains at a corner where the patterned silicon layer interfaces with the buried insulator layer. An oxide liner is formed on the exposed sidewall portion. A recess may be formed in the buried insulator layer (prior to forming the first layer) and may extend partially beneath the patterned silicon layer.Type: GrantFiled: September 7, 2005Date of Patent: February 19, 2008Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuang-Hsin Chen, Hsun-Chih Tsao, Hung-Wei Chen, Di-Hong Lee, Chuan-Ping Hou, Jhi-Cherng Lu
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Publication number: 20070272954Abstract: A fin-FET device and a method for fabrication thereof both employ a bulk semiconductor substrate. A fin and an adjoining trough are formed within the bulk semiconductor substrate. The trough is partially backfilled with a deposited dielectric layer to form an exposed fin region and an unexposed fin region. A gate dielectric layer is formed upon the exposed fin region and a gate electrode is formed upon the gate dielectric layer. By employing a bulk semiconductor substrate the fin-FET device is fabricated cost effectively.Type: ApplicationFiled: May 27, 2006Publication date: November 29, 2007Inventors: Kuang-Hsin Chen, Hsun-Chih Tsao, Jhi-Cherng Lu, Chuan-Ping Hou, Peng-Fu Hsu, Hung-Wei Chen, Di-Hong Lee
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Patent number: 7265425Abstract: A semiconductor device formed on a semiconductor substrate and a method of forming the same. In one embodiment, the semiconductor device includes a gate over the semiconductor substrate and a dielectric liner on a sidewall of the gate. The semiconductor device also includes an extension spacer adjacent and extending laterally beyond the dielectric liner along the semiconductor substrate. The semiconductor device further includes a source/drain located below an upper surface of the semiconductor substrate and adjacent a channel region under the gate. The source/drain extends under the dielectric liner and the extension spacer. The semiconductor device still further includes a silicide region over a portion of the source/drain and extending laterally beyond the extension spacer along the semiconductor substrate. Thus, the extension spacer is interposed between the dielectric liner and the silicide region located over a portion of the source/drain.Type: GrantFiled: November 15, 2004Date of Patent: September 4, 2007Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuang-Hsin Chen, Tang-Xuan Zhong, Chien-Chao Huang, Cheng-Kuo Wen, Di-Hong Lee
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Patent number: 7205601Abstract: A FinFET split gate EEPROM structure includes a semiconductor substrate and an elongated semiconductor fin extending above the substrate. A control gate straddles the fin, the fin's sides and a first drain-proximate portion of a channel between a source and drain in the fin. The control gate includes a tunnel layer and a floating electrode over which are a first insulative stratum and a first conductive stratum. A select gate straddles the fin and its sides and a second, source-promixate portion of the channel. The select gate includes a second insulative stratum and a second conductive stratum. The insulative strata are portions of a continuous insulative layer covering the substrate and the fin. The conductive strata are electrically continuous portions of a continuous conductive layer formed on the insulative layer.Type: GrantFiled: June 9, 2005Date of Patent: April 17, 2007Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Di-Hong Lee, Hsun-Chih Tsao, Kuang-Hsin Chen, Hung-Wei Chen
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Publication number: 20060278915Abstract: A FinFET split gate EEPROM structure includes a semiconductor substrate and an elongated semiconductor fin extending above the substrate. A control gate straddles the fin, the fin's sides and a first drain-proximate portion of a channel between a source and drain in the fin. The control gate includes a tunnel layer and a floating electrode over which are a first insulative stratum and a first conductive stratum. A select gate straddles the fin and its sides and a second, source-promixate portion of the channel. The select gate includes a second insulative stratum and a second conductive stratum. The insulative strata are portions of a continuous insulative layer covering the substrate and the fin. The conductive strata are electrically continuous portions of a continuous conductive layer formed on the insulative layer.Type: ApplicationFiled: June 9, 2005Publication date: December 14, 2006Inventors: Di-Hong Lee, Hsun-Chih Tsao, Kuang-Hsin Chen, Hung-Wei Chen
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Publication number: 20060214226Abstract: A semiconductor device and method for forming the same including improved electrostatic discharge protection for advanced semiconductor devices, the semiconductor device including providing semiconductor substrate having a pre-selected surface orientation and crystal direction; an insulator layer overlying the semiconductor substrate; a first semiconductor active region overlying the insulator layer having a first surface orientation selected from the group consisting of <100> and <110>; a second semiconductor active region extending through a thickness portion of the insulator layer having a second surface orientation selected from the group consisting of <110> and <100> different from the first surface orientation; wherein MOS devices including a first MOS device of a first conduction type is disposed on the first semiconductor active region and a second MOS device of a second conduction type is disposed on the second semiconductor active region.Type: ApplicationFiled: March 23, 2005Publication date: September 28, 2006Inventors: Hung-Wei Chen, Hsun-Chih Tsao, Kuang-Hsin Chen, Di-Hong Lee
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Publication number: 20060102955Abstract: A semiconductor device formed on a semiconductor substrate and a method of forming the same. In one embodiment, the semiconductor device includes a gate over the semiconductor substrate and a dielectric liner on a sidewall of the gate. The semiconductor device also includes an extension spacer adjacent and extending laterally beyond the dielectric liner along the semiconductor substrate. The semiconductor device further includes a source/drain located below an upper surface of the semiconductor substrate and adjacent a channel region under the gate. The source/drain extends under the dielectric liner and the extension spacer. The semiconductor device still further includes a silicide region over a portion of the source/drain and extending laterally beyond the extension spacer along the semiconductor substrate. Thus, the extension spacer is interposed between the dielectric liner and the silicide region located over a portion of the source/drain.Type: ApplicationFiled: November 15, 2004Publication date: May 18, 2006Inventors: Kuang-Hsin Chen, Tang-Xuan Zhong, Chien-Chao Huang, Cheng-Kuo Wen, Di-Hong Lee
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Publication number: 20060012004Abstract: In a method of manufacturing a semiconductor device, an initial structure is provided. The initial structure includes a substrate, a patterned silicon layer, and a covering layer. The substrate has a buried insulator layer formed thereon. The patterned silicon layer is formed on the buried insulator layer. The covering layer is formed on the patterned silicon layer. A first layer is formed on the initial structure. Part of the first layer is removed with an etching process, such that a sidewall portion of the patterned silicon layer is exposed and such that a remaining portion of the first layer remains at a corner where the patterned silicon layer interfaces with the buried insulator layer. An oxide liner is formed on the exposed sidewall portion. A recess may be formed in the buried insulator layer (prior to forming the first layer) and may extend partially beneath the patterned silicon layer.Type: ApplicationFiled: September 7, 2005Publication date: January 19, 2006Inventors: Kuang-Hsin Chen, Hsun-Chih Tsao, Hung-Wei Chen, Di-Hong Lee, Chuan-Ping Hou, Jhi-Cherng Lu
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Publication number: 20050275010Abstract: Nano-wires, preferably of less than 20 nm diameter, can be formed with minimized risk of narrowing and breaking that results from silicon atom migration during an annealing process step. This is accomplished by masking portion of the active layer where silicon atomer would otherwise agglomerate with a material such as silicon dioxide, silicon nitride, or other dielectric that eliminates or substantially reduces the silicon atom migration. Nano-wires, nanotubes, nano-rods, and other features can be formed and can optionally be incorporated into devices, such as by use as a channel region in a transistor device.Type: ApplicationFiled: April 12, 2005Publication date: December 15, 2005Inventors: Hung-Wei Chen, Yee-Chia Yeo, Di-Hong Lee, Fu-Liang Yang, Chenming Hu
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Publication number: 20050242398Abstract: An integrated circuit comprises a substrate and a buried dielectric formed in the substrate. The buried dielectric has a first thickness in a first region, a second buried dielectric thickness in a second region, and a step between the first and second regions. A semiconductor layer overlies the buried dielectric.Type: ApplicationFiled: March 29, 2005Publication date: November 3, 2005Inventors: Hao-Yu Chen, Chang-Yun Chang, Di-Hong Lee, Fu-Liang Yang
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Patent number: 6955955Abstract: In a method of manufacturing a semiconductor device, an initial structure is provided. The initial structure includes a substrate, a patterned silicon layer, and a covering layer. The substrate has a buried insulator layer formed thereon. The patterned silicon layer is formed on the buried insulator layer. The covering layer is formed on the patterned silicon layer. A first layer is formed on the initial structure. Part of the first layer is removed with an etching process, such that a sidewall portion of the patterned silicon layer is exposed and such that a remaining portion of the first layer remains at a corner where the patterned silicon layer interfaces with the buried insulator layer. An oxide liner is formed on the exposed sidewall portion. A recess may be formed in the buried insulator layer (prior to forming the first layer) and may extend partially beneath the patterned silicon layer.Type: GrantFiled: December 29, 2003Date of Patent: October 18, 2005Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuang-Hsin Chen, Hsun-Chih Tsao, Hung-Wei Chen, Di-Hong Lee, Chuan-Ping Hou, Jhi-Cherng Lu
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Publication number: 20050145937Abstract: In a method of manufacturing a semiconductor device, an initial structure is provided. The initial structure includes a substrate, a patterned silicon layer, and a covering layer. The substrate has a buried insulator layer formed thereon. The patterned silicon layer is formed on the buried insulator layer. The covering layer is formed on the patterned silicon layer. A first layer is formed on the initial structure. Part of the first layer is removed with an etching process, such that a sidewall portion of the patterned silicon layer is exposed and such that a remaining portion of the first layer remains at a corner where the patterned silicon layer interfaces with the buried insulator layer. An oxide liner is formed on the exposed sidewall portion. A recess may be formed in the buried insulator layer (prior to forming the first layer) and may extend partially beneath the patterned silicon layer.Type: ApplicationFiled: December 29, 2003Publication date: July 7, 2005Inventors: Kuang-Hsin Chen, Hsun-Chih Tsao, Hung-Wei Chen, Di-Hong Lee, Chuan-Ping Hou, Jhi-Cherng Lu